Preliminary Technical Information

AD6426

This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no

obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any

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Revision Preliminary 2.3 (June 9, ´98)

- 41 -

Confidential Information

TIMING CHARACTERISTICS

EVBC Interface VSPORT

Parameter

Comment (see Figure 21)

Min

Typ

Max

Units

VSCLK period

76.9

ns

VSFS setup time before VSCLK low

4

ns

VSFS hold time after VSCLK low

7

ns

VSDI setup time before VSCLK low

4

ns

VSDI hold time after VSCLK low

7

ns

VSDO delay after VSCLK high

0

15

ns

VSCLK (I)

VSDI (I)

VSDO (O)

D15

D14

VSFS (I)

t

93

D15

D14

D13

Figure 21. EVBC Interface VSPORT Timing