Preliminary Technical Information

AD6426

This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no

obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any

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rights of Analog Devices.

Revision Preliminary 2.3 (June 9, ´98)

- 14 -

Confidential Information

GENERAL CONTROL

Clocks

Clock Input

The AD6426 requires a single 13 MHz, low level clock signal,

which has to be provided at the pin CLKIN. For proper

This feature eases system design and reduces the need for

external clock buffering. Only minimal external components

are required as shown in Figure 4.

The internal clock buffer can accept any regular waveform as

long as it can find voltage points in the signal, for which a

50% duty cycle can be determined. This condition is met for

sinewaves, triangles, or slew-limited square waves. Dedicated

circuitry searches for these points and generates the respective

bias voltage internally.

The external capacitor (1nF) decouples the bias voltage of the

clock signal generated by the oscillator from the internally

generated bias voltage of the clock buffer circuitry.

The LC-filter shown is optional. It ensures, that the input

signal is “well behaved” and sinusoidal. Additionally it filters

out harmonics and noise, that may be on top of the pure 13

MHz signal.

13 MHz

VCTCXO

AD6422

OUT

CLKIN

1nF

2.2

µH

68 pF

Optional

13 MHz Filter

Figure 4. Clock Input Circuitry

Clock Output

The input clock drives both the H8 and the Channel Codec

directly. A gated version, controlled by the Output Clock

Enable flag in CC Control Register 45, drives the CLKOUT

pin of the EVBC interface. The stand-by state of CLKOUT is

logic zero. The CLKOUT output will be active on reset.

Slow Clocking

To reduce power consumption of AD20msp425 solutions, a

new slow clocking scheme has been designed into the

AD6426. This scheme allows the VCTCXO to be powered

down between paging blocks during Idle Mode and for a

32.768kHz oscillator to keep the time reference during this

period. Only a common 32.768kHz watch crystal is required to

take advantage of this scheme. As in previous generations,

power consumption is also kept to a minimum using

asynchronous design techniques and by stopping all

unnecessary clocks.

Layer 1 software and logic built into the AD6426 are

responsible for maintaining synchronization and calibration of

the slow clock and ensure the validity of the time reference

under all circumstances. The active-high OSC13MON output

is prevented from becoming inactive if the 32.768kHz signal is

not present. The following table describes the functionality of

the relevant pins.

Name

I/O

Function

OSCIN

I

32.768kHz Crystal Input

OSCOUT

O

32.768kHz Oscillator

Output

OSC13MON

O

13 MHz Oscillator Power

Control

PWRON

O

Power ON/OFF Control

The following table lists the recommended specification for a

32kHz crystal.

Parameter

Min

Typ

Max

Units

ESR

50

k

Ω

Shunt Capacitance

2

pF

Load Capacitance

6

12.5

30

pF

Turnover

25

°C

Parabolic Curvature

Constant (K)

0.040

ppm/°C

Real Time Clock and Alarm

The AD6426 provides a simple Real Time Clock (RTC) using

the 32.768kHz clock input. A 40 bit counter allows for more

than one year of resolution. The RTC module contains a

32.768kHz on chip oscillator buffer designed for very low

power consumption and a set of registers for a timer, alarm,

control and status functions.

The RTC circuit is supplied by two sources; a VDDRTC

supply pin and the main system VDD. It is the handset

designer’s responsibility to provide suitable switching

between the main system VDD and a backup supply to ensure

the RTC module is permanently powered.

The VDDRTC pin is intended to interface to a backup battery

circuit or charge holding network in order for the RTC to

maintain timing accuracy when the main battery is removed

and the handset is powered down.

The user can set an alarm time at which the handset powers

up. If an alarm time is set, the current time matches the alarm

time, and the power on alarm feature is enabled, the handset is

powered up by asserting the PWRON pin for a period of

approximately 2 seconds.