Preliminary Technical Information

AD6426

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Revision Preliminary 2.3 (June 9, ´98)

- 22 -

Confidential Information

Radio Interface

The AD6426 Radio Interface has been designed to support

direct connection to the ADI IF-Chips AD6432, while

providing full backwards compatibility to existing radio

designs interfacing to the AD20msp410 and AD20msp415.

Additionally the AD6426 Radio Interface supports radio

architectures based on Siemens, TTP/Hitachi or Philips RF

chipsets.

The Radio Interface of the AD6426 consists of 16 dedicated

output pins listed in Table 13. Together with two optional

general purpose I/O-pins they provide a flexible interface to a

variety of radio architectures for both 900 MHz and 1800/1900

MHz operation.

Dual Band Control

To support dual band handsets BANDSELECT[1:0] signals

are provided. BANDSELECT0 is multiplexed with GPIO[2],

with the default function of this being GPIO[2].

BANDSELECT1 is multiplexed with GPIO[1], the default

function being GPIO[1].

For Dual Band solutions requiring a single band select bit, the

BANDSELECT0 function is enabled by asserting the BAND

EN bit. In order to set BANDSELECT0 high/low and cause

the radio module to operate in the appropriate band, the least

significant bit (bit 0) of the relevant 32 bit register for

Dynamic Synthesizer 1 must be written, i.e. different values

may be set for Rx, Tx and Monitor but only for Dynamic

Synthesizer 1.

BANDSELECT0 is sampled internally and is valid from the

beginning of data serialization, both for on demand

(immediate) loading and ordinary interrupt driven loading.

The BANDSELECT0 signal will remain in this known state

until the next time there is any serialization of data for

Dynamic Synthesizer 1, when a new sample will be taken of

the least significant bit of the 32 bit synthesizer register

currently being serialized.

Full control is provided over the number of bits to be shifted

out to the synthesizer and so it is intended that this bit count

will always be less than 32 when using the BANDSELECT0

feature in order to prevent shifting the control bit out.

BANDSELECT0 is gated with RADIO POWER CONTROL to

ensure that whenever the RADIO is off, BANDSELECT0 is

forced to a low state.

For Dual Band Solution requiring two band select bits, one for

GSM900, and one for DCS1800, then both BANDSELECT0

and BANDSELECT1 are enabled by asserting both the BAND

EN and DCSSEL EN bits. The BANDSELECT0 output is

driven as in the single enable mode (described above), and the

BANDSELECT1 output is the inverted output of the raw

BANDSELECT0 output (prior to gating with RADIO POWER

CONTROL), gated with RADIO POWER CONTROL to force

a low output when the Radio is off.

In order to increase the flexibility of the AD6426, three pins in

the Radio Interface are multiplexed with GPO functions. The

pins multiplexed are: SYTHEN1, AGCA and AGCB, with the

default function being the Radio Interface.

The mode of these pins is controlled by the new ccGPO

Channel Codec Register:

The GPO[n]Sel bit selects the function of the pin. Setting

GPO[n]Sel to one will enable the pin to be controlled by the

GPO[n] bit. The GPO[n]Sel bit will override any other pin

function selection.

Generic Pins

The following three pins have the same functionality in all

types of radio architectures:

RADIOPWRCTL

This output signal is typically used to power down the

oscillators and prescalers during Idle mode and is directly

controlled by the Radio Power Control flag in the POWER

CONTROL EXTERNAL CC Control Register 45.

Bit

POWER CONTROL EXTERNAL CC Control

Register 45

1

Radio Power Control

Table 13. Radio Interface

Name

I/O

Function

GPIO1

O

BANDSELECT1

GPIO2

O

BANDSELECT0

RADIOPWRCTL

O

Radio Powerdown Control

GPIO6

O

VBIAS

GPIO7

O

ANTENNASELECT

TXPHASE

O

Switches PLLs (Rx / Tx)

TXENABLE

O

Transmit Enable

TXPA

O

Power Amplifier Enable

RXON

O

Receiver on

CALIBRATERADIO

O

Radio Calibration

SYNTHEN0

O

Synthesizer 0 Enable

SYNTHEN1

O

Synthesizer 1 Enable

SYNTHDATA

O

Synthesizer Port Serial Data

SYNTHCLK

O

Synthesizer Port Clock

AGCA

O

AGC Control A

AGCB

O

AGC Control B