Preliminary Technical Information

AD6426

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Revision Preliminary 2.3 (June 9, ´98)

- 26 -

Confidential Information

In Modes 2 and 3, PLL programming occurs on any of Rx, Tx

and MonEnableEnd through the synthesizer interface.

Additionally, AGC programming, controlled via the DSP, is

performed during RXON.

Table 18. Pin Function in Mode 2

AD6426 Pin

Function

AGCA

DSPFLAG0 ô SYNTHEN1

AGCB

DSPFLAG1

The third mode is for support of the Siemens chipset,

providing an independent AGC enable from SYNTHEN using

the DSP Flag 0. The same serial interface constraints from

Mode 2 apply. Additionally, the output OCE is provided. This

is the Offset Correction Enable, derived from the

RxEnableStartEarly and RxEnableStartLate timing signals as

shown in Figure 9.

Table 19. Pin Function in Mode 3

AD6426 Pin

Function

AGCA

DSPFLAG0

AGCB

OCE

RxEnableStartEarly

RxEnableStartLate

RXON

OCE

Figure 9. OCE Signal