ADMC401 datasheet(40/60 Pages) AD

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REV. B

ADMC401

–40–

edge on any of them will instantaneously shut down the PWM.

However, based on the particular PIO interrupt that is flagged,

the user can easily determine the source of the shutdown. This

permits the action of the interrupt service routines following a

PWM shutdown to be tailored to the particular fault that occurred.

On reset, all PIO lines are configured as PWM shutdown sources.

Because all PIO lines are also configured as inputs and have

internal pull-down resistors, any unconnected PIO lines will

cause a PWM shutdown. Therefore, prior to using the PWM

system of the ADMC401, it is imperative that the PIO stage be

correctly configured for the particular application.

PIO REGISTERS

The configuration of all registers associated with the PIO system

of the ADMC401 are shown at the end of the data sheet. Each

of the registers has a bit directly associated with one of the PIO

lines. For example, Bit 0 of all registers affects only the PIO0

line of the ADMC401.

EVENT TIMERS

OVERVIEW

The ADMC401 contains a dual channel event timer (capture)

unit (ETU) that may be used to accurately measure the elapsed

time between defined instants on a particular channel. The ETU

has two dedicated input pins, ETU0 and ETU1. The ETU

system contains a set of 16-bit data registers that are used to

store the value of the dedicated ETU timer on the occurrence of

defined events on the input pins. A configuration register is used

to define the nature of the events on each of the input pins. In

addition, a control register is used to initiate event capture on

the inputs. A status register may be read to determine the state

of the two capture channels. A dedicated ETU interrupt may be

generated upon completion of a capture sequence on either the

ETU0 or ETU1 channels. An event may be defined as either a

rising or falling edge on the associated ETU0 and ETU1 input

pins. Therefore, the ETU system can be used to compute the

frequency, period, duty cycle or on-time of signals applied at the

inputs. A block diagram of the ETU system of the ADMC401 is

shown in Figure 32.

ETUA0(15…0)

ETUB0(15…0)

ETUAA0(15…0)

ETUDIVIDE(15…0)

ETUTIME(15…0)

ETUCONFIG(7…0)

ETUCTRL(1…0)

ETUSTAT(1…0)

ETUA1(15…0)

ETUB1(15…0)

ETUAA1(15…0)

CAPTURE CHANNEL 0

ETU TIMER

EVENT

DETECTOR

EVENT

DETECTOR

CAPTURE CHANNEL 1

ETU0

ETU1

Figure 32. Functional Block Diagram of Event Timer Unit

of ADMC401

ETU EVENT DEFINITION

The ETU system of the ADMC401 contains a dedicated 16-bit

timer whose clock frequency may be programmed using the

ETUDIVIDE register. This register divides the CLKOUT

frequency to provide the clock signal for the ETU timer.

The clock frequency of the ETU timer may be expressed as

fCLKOUT/ETUDIVIDE and is common to both channels. At any

time, the contents of the ETU timer may be read in the 16-bit

read only ETUTIME register.

Two events are used to trigger the ETU, termed Event A and

Event B. By setting the appropriate bits of the ETUCONFIG

rising or falling edges on the appropriate pin. For example,

setting Bit 0 of the ETUCONFIG register defines Event A of

the ETU0 channel as a rising edge on the ETU0 pin. Similarly,

setting Bit 4 of the ETUCONFIG register defines Event A of

the ETU1 channel as a rising edge on the ETU1 pin. Event A

defines the start of the event capture sequence. Associated with

each ETU channel are three data registers, ETUA0, ETUB0

and ETUAA0 for ETU Channel 0 and ETUA1, ETUB1 and

ETUAA1 for ETU Channel 1. These data registers store the

ETU timer value on the occurrence of the first A event, the first

B event and the second A event, respectively. For example, for

ETU Channel 0, ETUA0 stores the timer value on the first

occurrence of Event A on the ETU0 pin, ETUB0 stores the

timer value on the first occurrence of Event B on the ETU0 pin

and ETUAA0 store the timer value on the second occurrence

of Event A on the ETU0 pin. Registers ETUA1, ETUB1 and

ETUAA1 perform the same function for events on ETU

Channel 1.

ETU INTERRUPT GENERATION

The completion of the event capture sequence can be defined as

either the occurrence of Event B or the second occurrence of

Event A by setting the appropriate bits of the ETUCONFIG

an interrupt. For example, if Bit 2 of the ETUCONFIG register

is set, ETU Channel 0 will generate an ETU interrupt on the

occurrence of Event B on the ETU0 pin. On the other hand, if

Bit 6 of the ETUCONFIG register is cleared, ETU Channel 1

will generate an ETU interrupt on the occurrence of the second

Event A on the ETU1 pin. Both ETU channels generate the

same interrupt to the DSP when capture is complete. If both

ETU channels are used simultaneously, the ETUSTAT register

can be polled to determine the status of both channels and

determine which caused the interrupt. If capture on ETU Chan-

nel 0 is complete, Bit 0 of the ETUSTAT register is set. Simi-

larly, if event capture on ETU Channel 1 is complete, Bit 1 of

the ETUSTAT register is set. Reading the ETUSTAT register

automatically clears all bits of the register.

ETU OPERATING MODES

The ETU channels of the ADMC401 can operate in two dis-

tinct modes; single shot and free-running. The particular mode

may be selected for ETU Channel 0 by programming Bit 3 of

the ETUCONFIG register and for ETU Channel 1 by program-

ming Bit 7 of the ETUCONFIG register. Setting these bits puts

the respective ETU channel in free-running mode while clearing

the bits enables the single-shot mode. In single-shot mode, upon

completion of the capture sequence and consequent generation

of the interrupt, further event capture is disabled until the inter-

rupt has been serviced and the appropriate bit of the ETUCTRL

restarts the capture for ETU Channel 0, while Bit 1 restarts

capture for Channel 1. In the free-running mode, the bits of the

ETUCTRL register remain set and the ETU channel continues

to capture following the generation of the interrupt.

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