ADMC401 datasheet(53/60 Pages) AD

53 / 60 page

ADMC401

–53–

REV. B

DM (0x2011)

ADC END OF CONVERSION

PWMSYNC

EIU LOOP TIMER TIMEOUT

PIO4 - PIO11 INTERRUPT

EIU COUNT ERROR INTERRUPT

DM (0x201D)

PICMASK (R/W)

000

DM (0x2012)

DM (0x2013)

0 = DISABLE INTERRUPT (MASK)

1 = ENABLE INTERRUPT

PWM TRIP INTERRUPT

PIO3 INTERRUPT

PIO2 INTERRUPT

PIO1 INTERRUPT

PIO0 INTERRUPT

ETU INTERRUPT

AUXCH0 (R/W)

DM (0x2010)

TON, AUX0 = 2

AUXCH0

tCK

AUXTM0 (R/W)

AUXTM1 (R/W)

TAUX1 = 2

AUXCH1

tCK

TON, AUX0 = 2

(AUXTM0+1)

tCK

TAUX1 = 2

(AUXTM1+1)

tCK IN INDEPENDENT MODE

TOFFSET = 2

(AUXTM1+1)

tCK IN OFFSET MODE

AUXCH1 (R/W)

Figure 41. Structure of Registers of ADMC401

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—

these bits should always be written as shown.

ADMC401 Datasheet(PDF) 53 Page - Analog Devices

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