ADMC401 datasheet(24/60 Pages) AD

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REV. B

ADMC401

–24–

CONVERT START COMMAND

The analog-to-digital conversion process of the ADMC401 may

be started by either an internal or an external command. Bit 0 of

the ADCCTRL register determines whether internal or external

convert start mode is enabled. If Bit 0 of the ADCCTRL regis-

ter is cleared, internal convert start mode is selected, and the

ADC conversion process is started on the rising edge of the

PWMSYNC signal. This results in one conversion sequence per

PWM switching period (at the start of each period) when the

PWM generation unit operates in the single update mode. In the

double update operating mode, there are two conversion se-

quences per PWM switching period (one at the start and one in

the middle of each period). In internal convert start mode, in

order to ensure correct synchronization and jitter-free operation,

it is essential that the value written to the PWMTM register be a

multiple of four. In other words, the two LSBs of the value

written to the PWMTM register must both be 0.

If Bit 0 of the ADCCTRL register is set, external convert start

mode is selected. In this mode, the conversion process is started

on the occurrence of a rising edge on the CONVST pin. Addi-

tionally, the start of conversion can be placed under software

control by externally connecting one of the programmable input/

output (PIO) lines to the CONVST pin and generating a rising

edge by writing to the appropriate bit of the PIODATA register.

By default, following reset, Bit 0 of the ADCCTRL register is

cleared so that internal convert start mode is selected.

ADC CLOCK SIGNALS

The ADC consists of a pipeline flash architecture and is clocked

at a quarter of the DSP instruction rate. All of the timing of the

ADC system (including control of the multiplexers and sample

and hold amplifiers) is regulated by this clock signal and it de-

termines the total conversion time for all of the channels as well

as the delay between sampling of successive pairs of analog

inputs. The ADC clock rate is internally fixed and may not be

changed. The period of the ADC clock, tCKADC is related to the

DSP CLKOUT period by:

CKADC

=×

A DSP rate of 26 MHz corresponds to a tCKADC of approxi-

mately 154 ns.

ANALOG INPUT CONFIGURATION AND OVERVIEW

Figure 17 is a simplified model of the ADC input structure for

one channel (VIN0) of the ADC system of the ADMC401. This

model applies to all eight input channels. The internal multi-

plexers are used to switch the various analog inputs to the A/D

converter. For analog inputs VIN0 to VIN3, there is a single

common terminal (ASHAN) that is the inverting input to the

internal differential sample and hold amplifier. For the input

signals, VIN4 to VIN7, the equivalent input is BSHAN. The

value VREF (internally generated voltage reference or externally

applied voltage reference on the VREF pin) defines the maximum

input voltage to the A/D core. The minimum input voltage to

the A/D core is automatically defined as –VREF.

+VREF

–VREF

VIN0

ASHAN

VCORE

A/D

CORE

Figure 17. Equivalent Functional Input Circuit of ADC

System

The dc voltage on the VREF pin sets the common-mode voltage

of the A/D converter of the ADMC401. For example, when

using the internal 2.0 V reference, the input level will also be

centered about 2.0 V. The ADC inputs of the ADMC401 can

be configured for single ended operation, where the inverting

terminals (ASHAN and BSHAN) are connected directly to the

reference voltage level, and the analog inputs (VIN0 to VIN7)

are driven by analog signals with a 4.0 V p-p range. The VIN0

to VIN7 inputs are unipolar so that when operating from the

internal 2.0 V reference, these signals can range from 0 V to

4 V. The recommended single-ended input configuration for a

single analog input channel of the ADMC401 is shown in Fig-

ure 18. The input to the A/D converter must be driven by an

operational amplifier with sufficient drive strength so that the

A/D performance is not degraded. Sufficient drive strength is

the ability to drive a load of 6 pF static and 4 pF switched from

ground (capacitive) to settle within

±1.0 mV within 70 ns. In

Figure 18, the operational amplifier is shown configured as a

simple noninverting input buffer. Of course, the operational

amplifier stage could also be used to implement any necessary

level shifting and/or filtering of the input signal.

–V

VIN0

ASHAN

VREF

SENSE

ADMC401

10 F

0.1 F

Figure 18. Typical Single-Ended Input Configuration for

ADMC401

From Figure 17, it is clear that the input to the A/D core is

simply given by:

VIN

ASHAN

CORE

0–

which must satisfy the condition:

–VV

REF

CORE

REF

≤≤

where VREF is the voltage at the VREF pin of the ADMC401

(either internally generated or externally supplied). There is an

additional limit placed on the valid operating range for the VIN0

and ASHAN inputs that is bounded by the power supply of the

ADMC401:

VIN

ASHAN

–.

0 3

≤≤

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