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ADMC401 Datasheet(PDF) 55 Page - Analog Devices |
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ADMC401 Datasheet(HTML) 55 Page - Analog Devices |
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55 / 60 page ![]() ADMC401 –55– REV. B TIMER SPORT1 RECEIVE or IRQ0 SPORT1 TRANSMIT or IRQ1 SOFTWARE 0 SOFTWARE 1 SPORT0 RECEIVE SPORT0 TRANSMIT IRQ2 IRQ2 SPORT0 TRANSMIT SPORT0 RECEIVE SOFTWARE1 SOFTWARE 0 SPORT1 TRANSMIT OR IRQ1 SPORT1 RECEIVE OR IRQ0 TIMER INTERRUPT FORCE INTERRUPT CLEAR IFC (R/W) 98 7654321 0 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 000 IRQ0 SENSITIVITY IRQ1 SENSITIVITY IRQ2 SENSITIVITY INTERRUPT NESTING 1 = ENABLE, 0 = DISABLE 0 ICNTL (R/W) 1 = EDGE 0 = LEVEL 43 210 10 11 12 13 14 15 98 76 543 21 0 IRQ2 HIP WRITE HIP READ SPORT0 TRANSMIT SPORT0 RECEIVE IMASK (R/W) DSP REGISTER 1 = ENABLE, 0 = DISABLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER IRQ0 or SPORT1 RECEIVE IRQ1 or SPORT1 TRANSMIT SOFTWARE 0 SOFTWARE 1 DSP REGISTER DSP REGISTER Figure 43. Structure of Registers of ADMC401 Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these bits should always be written as shown. |
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