ADMC401 datasheet(56/60 Pages) AD

56 / 60 page

REV. B

ADMC401

–56–

DM (0x3FFC)

TPERIOD (R/W)

TCOUNT (R/W)

TSCALE (R/W)

DM (0x3FFD)

DM (0x3FFB)

9876543210

SSTAT (R)

PC STACK EMPTY

PC STACK OVERFLOW

COUNT STACK EMPTY

COUNT STACK OVERFLOW

STATUS STACK EMPTY

STATUS STACK OVERFLOW

LOOP STACK EMPTY

LOOP STACK OVERFLOW

543

MSTAT (R/W)

6543210

DSP REGISTER

DATA REGISTER BANK SELECT

0 = PRIMARY, 1 = SECONDARY

BIT REVERSE MODE ENABLE (DAG1)

ALU OVERFLOW LATCH MODE ENABLE

AR SATURATION MODE ENABLE

MAC RESU PLACEMENT

0 = FRACTIONAL,LT 1 = INTERGER

TIMER ENABLE

GO MODE ENABLE

SYSCNTL (R/W)

PWAIT

PROGRAM MEMORY

WAIT STATES

9876543210

BPAGE

BOOT PAGE SELECT

BWAIT

BOOT WAIT STATES

BFORCE

BOOT FORCE BIT

SPORT0 ENABLE

1 = ENABLE, 0 = DISABLED

DM (0x3FFF)

SPORT1 ENABLE

1 = ENABLE, 0 = DISABLED

SPORT1 CONFIGURE

1 = SERIAL PORT

0 = FI, FO, IRQ0, IRQ1, SCLK

AZ ALU RESULT ZERO

AN ALU RESULT NEGATIVE

AV ALU OVERFLOW

AC ALU CARRY

AS ALU X INPUT SIGN

AQ ALU QUOTIENT

MV MAC OVERFLOW

SS SHIFTER INPUT SIGN

321

ASTAT (R/W)

DSP REGISTER

Figure 44 Structure of Registers of ADMC401

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these

bits should always be written as shown.

ADMC401 Datasheet(PDF) 56 Page - Analog Devices

ADMC401 Datasheet(HTML) 56 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Download

Link URL