ADMC401 datasheet(44/60 Pages) AD

44 / 60 page

REV. B

ADMC401

–44–

ROM or E

2PROM. Clearing the UARTEN bit selects SPORT

mode, so that SPORT1 is configured in a manner identical to

the standard serial ports of the ADSP-21xx family. Following

reset, the UARTEN bit is cleared so that SPORT mode is selected.

Bit 6 of the MODECTRL register is used to select between

single update and double update operating modes of the PWM

generation unit. Clearing this bit selects single update mode,

while setting it selects double update mode. Following reset,

this bit is cleared so that single update mode is the default

configuration.

Bit 8 of the MODECTRL register is used to select between

independent and offset operating modes of the auxiliary PWM

unit. Clearing this bit selects offset mode, while setting it selects

independent mode. Following reset, this bit is cleared so that

offset mode is the default configuration.

SYSSTAT REGISTER

The SYSSTAT register provides various status information of

the ADMC401, such as the state of the

PWMTRIP pin, the

state of the watchdog flag, the state of the PWMPOL pin and

phase of the PWM

Bit 0 indicates the state of the

PWMTRIP pin such that the bit

is set if

PWMTRIP is HI and cleared if the pin is LO. Similarly,

Bit 2 indicates the state of the PWMPOL pin such that the bit is

set if PWMPOL is HI (active high PWM selected) and cleared if

the pin is LO (active low PWM selected).

Bit 1 is used to indicate if a watchdog timer timeout has oc-

curred. This bit is set following a watchdog timeout and can be

read on reset to determine if the reset is a normal power-on

reset or due to a watchdog trip.

Bit 3 of the SYSSTAT register is used to identify the half cycle

of operation of the PWM generation unit. During the first half

cycle, when the internal PWM timer is decrementing, this bit is

cleared. During the second half cycle, this bit is set while the

timer is incrementing.

SYSTEM CONTROL REGISTERS

The configuration of the MODECTRL and SYSSTAT register

is shown at the end of the data sheet.

PERIPHERAL AND DSP CORE REGISTERS

The address, name, type, used bits and reset value of all of the

peripheral registers of the ADMC401 are given in Table VIII.

Similarly, the DSP core registers of the ADMC401 are tabu-

lated in Table IX.

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