ADMC401 datasheet(14/60 Pages) AD

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ADMC401

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Programmable Digital I/O (PIO) Port

12-Pin Configurable Digital I/O Port

Flexible Interrupt Generation

Four Dedicated PIO Interrupt Vectors

Each I/O Line Configurable as PWM Shutdown

Two 8-Bit Auxiliary PWM Outputs

Programmable Switching Frequency

Independent or Offset Modes

Two-Channel Event Timer (Capture) Unit

Configurable Event Definition

Single-Shot or Free-Running Modes

Peripheral Interrupt Controller

Manages Peripheral Interrupts

16-Bit Watchdog Timer

Internal Power-On Reset System

Programmable 16-Bit Interval Timer with Prescaler

Two Double Buffered Synchronous Serial Ports

Boot Load Protocols via SPORT1:

Synchronous E2PROM/SROM Booting

UART Boot Loader with Autobaud

Synchronous Master or Slave Boot Loader

Debugger Interface via SPORT1:

UART Interface with Autobaud

Synchronous Master or Slave Interface

Full Debugger for Program Development

Industrial Temperature Range –40 C to +85 C

Operating Voltage 5.0 V

Package: 144-Lead LQFP

GENERAL DESCRIPTION

The ADMC401 is a single-chip DSP-based controller, suitable

for high performance control of ac induction motors (ACIM),

permanent magnet synchronous motors (PMSM), brushless dc

motors (BDCM) and switched reluctance (SR) motors in indus-

trial applications. The ADMC401 integrates a 26 MIPS, fixed-

point DSP core with a complete set of motor control peripherals

that permits fast motor control in a highly integrated environment.

The DSP core of the ADMC401 is the ADSP-2171 which is

completely code compatible with the ADSP-21xx DSP family

(as well as other members of the integrated motor controllers of

the ADMC3xx family) and combines three computational units,

data address generators and a program sequencer. The computa-

tional units comprise an ALU, a multiplier/accumulator (MAC)

and a barrel shifter. The DSP core also adds instructions for bit

manipulation, squaring (x

2), biased rounding and global inter-

rupt masking. In addition, two flexible double-buffered, bidirec-

tional synchronous serial ports are included in the ADMC401.

The ADMC401 provides 2K

× 24-bit internal program memory

RAM, 2K

× 24-bit internal program memory ROM and 1K ×

16-bit internal data memory RAM. The program and data

memory RAM can be boot loaded through the serial port from

either a serial E

2PROM, through a UART connection (either

from external host microprocessor or from the Motion Control

Debugger) or via a synchronous serial interface from a host

microprocessor. Alternatively, the internal program and data

memory RAM may be booted from an external device across the

address and data buses. The program memory ROM includes a

monitor that adds software debugging features through the serial

port.

Additionally, the ADMC401 device adds significant external

memory and peripheral expansion capabilities by making avail-

able the full address and data bus of the DSP core. This feature

permits expansion of both external program and data memory

and means that the DSP core can address up to 14K

× 24 bits of

external program memory and up to 13K

× 16 bits of external

data memory.

The ADMC401 contains a number of special purpose, motor

control peripherals. The first is a high performance, 8-channel,

12-bit ADC system with dual channel simultaneous sampling

ability across 4 pair of inputs. An internal precision voltage refer-

ence is also available as part of the ADC system. In addition, a

three-phase, 16-bit, center-based PWM generation unit can be

used to produce high-accuracy PWM signals with minimal pro-

cessor overhead. The ADMC401 also contains a flexible incre-

mental encoder interface unit for position sensor feedback;

two adjustable-frequency auxiliary PWM outputs, 12 lines of

digital I/O; a 2-channel event capture system; a 16-bit watchdog

timer; two 16-bit interval timers (one of which can be linked to

the encoder interface unit) and an interrupt controller that man-

ages all peripheral interrupts. Finally, the ADMC401 contains

an integrated power-on-reset (POR) circuit that can be used to

generate the required reset signal for the device on power-on.

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