ADMC401 datasheet(57/60 Pages) AD

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ADMC401

–57–

REV. B

31 30 29 28 27 26 25 24 23 22

21 20 19 18 17 16

SPORT0_RX_WORDS1 (R/W)

1 = CHANNEL ENABLE

0 = CHANNEL IGNORED

DM (0x3FFA)

15 14 13 12

11 10

SPORT0_RX_WORDS0 (R/W)

DM (0x3FF9)

31 30 29 28 27 26 25 24 23 22

21 20 19 18 17 16

SPORT0_TX_WORDS1 (R/W)

1 = CHANNEL ENABLE

0 = CHANNEL IGNORED

DM (0x3FF8)

15 14 13 12

11 10

SPORT0_TX_WORDS0 (R/W)

DM (0x3FF7)

MEMWAIT (R/W)

DWAIT4

DWAIT0

DWAIT1

DWAIT2

DWAIT3

ROM ENABLE

1 = ENABLE

0 = DISABLE

9876543210

NOTE: IN STANDALONE MODE (MMAP = BMODE = 1)

THE ROM MONITOR WRITES 0x8000 TO THIS REGISTER.

DM (0x3FFE)

MULTICHANNEL ENABLE MCE

IINTERNAL SERIAL CLOCK GENERATION ISCLK

RECEIVE FRAME SYNC REQUIRED RFSR

RECEIVE FRAME SYNC WIDTH RFSW

MULTI CHANNEL FRAME DELAY MFD

ONLY IF MULTICHANNEL MODE ENABLED)

TRANSMIT FRAME SYNC REQUIRED TFSR

TRANSMIT FRAME SYNC WIDTH TFSW

SLEN SERIAL WORD LENGTH

DTYPE DATA FORMAT

00 = RIGHT JUSTIFY, ZERO-FILLED UNUSED MSBS

01 = RIGHT JUSTIFY, SIGN EXTEND INTO UNUSED MSBS

10 = COMPAND USING

-LAW

11 = COMPAND USING A-LAW

ITFS INTERNAL TRANSMIT FRAME SYNC ENABLE

(OR MCL MULTICHANNEL LENGTH; 1 = 32 WORDS, 0 = 24 WORDS

ONLY IF MULTICHANNEL MODE ENABLED)

INVRFS IINVERT RECEIVE FRAME SYNC

INVTFS INVERT TRANSMIT FRAME SYNC

(OR INVTDV INVERT TRANSMIT DATA VALID

ONLY IF MULTICHANNEL MODE ENABLED)

IRFS INTERNAL RECEIVE FRAME SYNC ENABLE

SPORT0_CTRL_REG (R/W)

9876543210

DM (0x3FF6)

Figure 45. Structure of Registers of ADMC401

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these

bits should always be written as shown.

ADMC401 Datasheet(PDF) 57 Page - Analog Devices

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