ADS5404 datasheet(4/40 Pages) TI

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ADS5402

SLAS936 – MARCH 2013

www.ti.com

PIN ASSIGNMENTS (continued)

I/O

DESCRIPTION

NAME

NUMBER

Chip enable – active high. Power down function can be controlled through SPI register

ENABLE

B11

assignment. Internal 50k

Ω pull up resistor to IOVDD.

SCLK

A12

Serial interface clock. Internal 50k

Ω pull-down resistor.

Bi-directional serial data in 3 pin mode (default). In 4-pin interface mode (register x00, D16),

SDIO

A11

I/O

the SDIO pin is an input only. Internal 50k

Ω pull-down.

SDENB

A13

Serial interface enable. Internal 50k

Ω pull-down resistor.

Uni-directional serial interface data in 4 pin mode (register x00, D16). The SDO pin is tri-

SDO

A10

stated in 3-pin interface mode (default). Internal 50k

Ω pull-down resistor.

TESTMODE

B13

–

Factory internal test, do not connect

DATA INTERFACE

P3, N3, P2, N2,

P1, N1, M4, M3,

M2, M1, L4, L3,

DA[11:0]P/N

ADC A Data Bits 11 (MSB) to 0 (LSB) in DDR output mode. Standard LVDS output.

L2, L1, K4, K3,

K2, K1, J4, J3,

J2, J1, H4, H3

E2, E1, D4, D3,

D2, D1, C4, C3,

C2, C1, B1, A1,

DB[11:0]P/N

ADC B Data Bits 11 (MSB) to 0 (LSB) in DDR output mode. Standard LVDS output.

B2, A2, B3, A3,

B4, A4, B5, A5,

B6, A6, B7, A7

DDR differential output data clock for Bus A. Register programmable to provide either rising

DACLKP/N

H2, H1

or falling edge to center of stable data nominal timing.

DDR differential output data clock for Bus B. Register programmable to provide either rising

DBCLKP/N

G2, G1

or falling edge to center of stable data nominal timing. Optionally Bus B can be latched with

DACLKP/N.

SYNCOUTP/N

F2, F1, P5, N5

Synchronization output signal for synchronizing multiple ADCs. Can be disabled via SPI.

Bus A, Overrange indicator, LVDS output. A logic high signals an analog input in excess of

OVRAP/N

M5, L5

the full-scale range. Optional SYNC output.

Bus B, Overrange indicator, LVDS output. A logic high signals an analog input in excess of

OVRBP/N

D5, C5

the full-scale range. Optional SYNC output.

E3, E4, F3, F4,

G3, G4, N4, N6,

–

Don’t connect to pin

N7, N10, P4, P6,

P7, P10

POWER SUPPLY

D12, E12, F12,

G12, H12, J12,

AVDD33

3.3V analog supply

K12, L12, N12,

P12

AVDDC

G14, H14

1.8V supply for clock input

D10, D11, E11,

F11, G11, H11,

AVDD18

1.8V analog supply

J11, K11, L10,

L11, N11, P11

A8, A9, B8, B9,

DVDD

C8, D8, L8, M8,

1.8V supply for digital block

N8, P8

C6, C7, D6, D7,

DVDDLVDS

1.8V supply for LVDS outputs

L6, L7, M6, M7

IOVDD

B10

1.8V for digital I/Os

GND

Ground

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