2kΩ

2kΩ

0.9V

CLKINP

CLKINN

CLKINP

CLKINN

0.1uF

0.1uF

R

T

R

T

0.1uF

Recommended differential clock driving circuit

ADS5402

www.ti.com

SLAS936 – MARCH 2013

FEATURES

POWER DOWN MODES

The ADS5402 can be configured via SPI write (address x37) to a stand-by, light or deep sleep power mode

which is controlled by the ENABLE pin. The sleep modes are active when the ENABLE pin goes low. Different

internal functions stay powered up which results in different power consumption and wake up time between the

two sleep modes.

Power Consumption Auto

Power Consumption Auto

Sleep mode

Wake up time

correction disabled

correction enabled

Complete Shut Down

2.5 ms

7mW

7mW

Stand-by

100µs

7mW

7mW

Deep Sleep

20µs

375mW

510mW

Light Sleep

2µs

690mW

820mW

TEST PATTERN OUTPUT

The ADS5402 can be configured to output different test patterns that can be used to verify the digital interface is

connected and working properly. To enable the test pattern mode, the high performance mode 1 has to be

disabled first via SPI register write. Then different test patterns can be selected by configuring registers x3C, x3D

and x3E. All three registers must be configured for the test pattern to work properly.

First set HP1 = 0 (Addr 0x01, D01)

Register Address

All 0s

All 1s

Toggle (0xAAA => 0x555)

Toggle (0xFFF => 0x000)

0x3C

0x8000

0xBFFC

0x9554

0xBFFC

0x3D

0x0000

0x3FFC

0x2AA8

0x0000

0x3E

0x0000

0x3FFC

0x1554

0x3FFC

Register

Custom Pattern

Address

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

x3C

1

0

0

0

x3D

0

0

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

x3E

0

0

0

0

For normal operation, set HP1 = 1 (Addr 0x01, D01) and 0x3C, 0x3D, 0x3E all to 0.

CLOCK INPUT

The ADS5402 clock input can be driven differentially with a sine wave, LVPECL or LVDS source with little or no

difference in performance. The common mode voltage of the clock input is set to 0.9V using internal 2k

Ω

resistors. This allows for AC coupling of the clock inputs. The termination resistors should be placed as close as

possible to the clock inputs in order to minimize signal reflections and jitter degradation.

Figure 37. Recommended Differential Clock Driving Circuit

Copyright © 2013, Texas Instruments Incorporated

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