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WM8903 Datasheet(PDF) 19 Page - Wolfson Microelectronics plc |
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WM8903 Datasheet(HTML) 19 Page - Wolfson Microelectronics plc |
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19 / 178 page ![]() Production Data WM8903 w PD, Rev 4.5, June 2012 19 SIGNAL TIMING REQUIREMENTS COMMON TEST CONDITIONS Unless otherwise stated, the following test conditions apply throughout the following sections: Ambient temperature = +25°C DCVDD = 1.2V DBVDD = AVDD = CPVDD = 1.8V DGND = AGND = CPGND = 0V Additional, specific test conditions are given within the relevant sections below. MASTER CLOCK Figure 1 Master Clock Timing Master Clock Timing PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT MCLK cycle time TMCLKY MCLKDIV2=1 40 ns MCLKDIV2=0 80 ns MCLK cycle time TMCLKY DCVDD 1.62V MCLKDIV2=0 54.25 ns MCLK duty cycle TMCLKDS 60:40 40:60 |
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