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ADV7281 Datasheet(PDF) 7 Page - Analog Devices |
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ADV7281 Datasheet(HTML) 7 Page - Analog Devices |
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7 / 32 page  Data Sheet ADV7281 Rev. A | Page 7 of 32 MIPI VIDEO OUTPUT SPECIFICATIONS (ADV7281-M AND ADV7281-MA ONLY) AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted. The CSI-2 clock lane of the ADV7281-M/ADV7281-MA remains in high speed (HS) mode even when the data lane enters low power (LP) mode. For this reason, some measurements on the clock lane that pertain to low power mode are not applicable. Unless otherwise stated, all high speed measurements were performed with the ADV7281-M/ADV7281-MA operating in interlaced mode and with a nominal 216 Mbps output data rate. Specifications guaranteed by characterization. Table 5. Parameter Symbol Test Conditions/Comments Min Typ Max Unit UNIT INTERVAL UI Interlaced Output 4.63 ns DATA LANE LP TX DC SPECIFICATIONS1 Thevenin Output High Level VOH 1.1 1.2 1.3 V Thevenin Output Low Level VOL −50 0 +50 mV DATA LANE LP TX AC SPECIFICATIONS1 Rise Time, 15% to 85% 25 ns Fall Time, 85% to 15% 25 ns Rise Time, 30% to 85% 35 ns Data Lane LP Slew Rate vs. CLOAD Maximum Slew Rate over Entire Vertical Edge Region Rising edge 150 mV/ns Falling edge 150 mV/ns Minimum Slew Rate 400 mV ≤ VOUT ≤ 930 mV Falling edge 30 mV/ns 400 mV ≤ VOUT ≤ 700 mV Rising edge 30 mV/ns 700 mV ≤ VOUT ≤ 930 mV Rising edge >0 mV/ns Pulse Width of LP Exclusive-OR Clock First clock pulse after stop state or last pulse before stop state 40 ns All other clock pulses 20 ns Period of LP Exclusive-OR Clock 90 ns CLOCK LANE LP TX DC SPECIFICATIONS1 Thevenin Output High Level VOH 1.1 1.2 1.3 V Thevenin Output Low Level VOL −50 0 +50 mV CLOCK LANE LP TX AC SPECIFICATIONS1 Rise Time, 15% to 85% 25 ns Fall Time, 85% to 15% 25 ns Clock Lane LP Slew Rate Maximum Slew Rate over Entire Vertical Edge Region Rising edge 150 mV/ns Falling edge 150 mV/ns Minimum Slew Rate 400 mV ≤ VOUT ≤ 930 mV Falling edge 30 mV/ns 400 mV ≤ VOUT ≤ 700 mV Rising edge 30 mV/ns 700 mV ≤ VOUT ≤ 930 mV Rising edge >0 mV/ns DATA LANE HS TX SIGNALING REQUIREMENTS See Figure 5 Low Power to High Speed Transition Stage t9 Time that the D0P pin is at VOL and the D0N pin is at VOH 50 ns t10 Time that the D0P and D0N pins are at VOL 40 + (4 × UI) 85 + (6 × UI) ns t11 t10 plus the HS-zero period 145 + (10 × UI) ns High Speed Differential Voltage Swing |V1| 140 200 270 mV p-p Differential Voltage Mismatch 10 mV Single-Ended Output High Voltages 360 mV Static Common-Mode Voltage Level 150 200 250 mV Static Common-Mode Voltage Mismatch 5 mV Dynamic Common Level Variations 50 MHz to 450 MHz 25 mV Above 450 MHz 15 mV |
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