ADV7281 datasheet(27/32 Pages) AD

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Data Sheet

ADV7281

Rev. A | Page 27 of 32

PCB LAYOUT RECOMMENDATIONS

The ADV7281/ADV7281-M/ADV7281-MA are high precision,

high speed, mixed-signal devices. To achieve maximum perfor-

mance from the parts, it is important to use a well-designed PCB.

This section provides guidelines for designing a PCB for use

with the ADV7281/ADV7281-M/ADV7281-MA.

ANALOG INTERFACE INPUTS

When routing the analog interface inputs on the PCB, keep

track lengths to a minimum. Use 75 Ω trace impedances when

possible; trace impedances other than 75 Ω increase the chance

of reflections.

POWER SUPPLY DECOUPLING

It is recommended that each power supply pin be decoupled

with 100 nF and 10 nF capacitors. The basic principle is to place

a decoupling capacitor within approximately 0.5 cm of each power

pin. Avoid placing the decoupling capacitors on the opposite

side of the PCB from the ADV7281/ADV7281-M/ADV7281-MA

because doing so introduces inductive vias in the path.

Place the decoupling capacitors between the power plane and

the power pin. Current should flow from the power plane to the

capacitor and then to the power pin. Do not apply the power

connection between the capacitor and the power pin. The best

approach is to place a via near, or beneath, the decoupling capaci-

tor pads down to the power plane (see Figure 19).

SUPPLY

GROUND

10nF

100nF

VIA TO SUPPLY

VIA TO GND

Figure 19. Recommended Power Supply Decoupling

It is especially important to maintain low noise and good

stability for the PVDD pin. Careful attention must be paid to

regulation, filtering, and decoupling. It is highly desirable to

provide separate regulated supplies for each circuit group

AVDD, DVDD, DVDDIO, PVDD, and MVDD. MVDD only applies to the

ADV7281-M/ADV7281-MA models.

Some graphic controllers use substantially different levels of

power when active (during active picture time) and when idle

(during horizontal and vertical sync periods). This disparity can

result in a measurable change in the voltage supplied to the analog

supply regulator, which can, in turn, produce changes in the regu-

lated analog supply voltage. This problem can be mitigated by

regulating the analog supply, or at least the PVDD supply, from a

different, cleaner power source, for example, from a 12 V supply.

Using a single ground plane for the entire board is also recom-

mended. Experience has shown that the noise performance is

the same or better with a single ground plane. Using multiple

ground planes can be detrimental because each separate ground

plane is smaller, and long ground loops can result.

VREFN AND VREFP PINS

Place the circuit associated with the VREFN and VREFP pins as

close as possible to the ADV7281/ADV7281-M/ADV7281-MA

and on the same side of the PCB as the part.

DIGITAL OUTPUTS

The ADV7281 digital outputs are INTRQ, LLC, P0:P7. The

ADV7281-M/ADV7281-MA are INTRQ, GPO0 to GPO2.

Minimize the trace length that the digital outputs must drive.

Longer traces have higher capacitance, requiring more current

and, in turn, causing more internal digital noise. Shorter traces

reduce the possibility of reflections.

Adding a 30 Ω to 50 Ω series resistor can suppress reflections,

reduce EMI, and reduce current spikes inside the ADV7281/

ADV7281-M/ADV7281-MA. If series resistors are used,

place them as close as possible to the pins of the ADV7281/

ADV7281-M/ ADV7281-MA. However, try not to add vias or

extra length to the output trace in an attempt to place the resistors

closer.

If possible, limit the capacitance that each digital output must

drive to less than 15 pF. This recommendation can be easily

accommodated by keeping traces short and by connecting the

outputs to only one device. Loading the outputs with excessive

capacitance increases the current transients inside the ADV7281/

ADV7281-M/ADV7281-MA, creating more digital noise on the

power supplies.

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