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Data Sheet

ADV7281

Rev. A | Page 23 of 32

MIPI CSI-2 OUTPUT

The decoder in the ADV7281-M/ADV7281-MA outputs an

ITU-R BT.656 data stream. The ITU-R BT.656 data stream is

connected into a CSI-2 Tx module. Data from the CSI-2 Tx

module is fed into a D-PHY physical layer and output serially

from the device.

The output of the ADV7281-M/ADV7281-MA consists of a

single data channel on the D0P and D0N lanes and a clock

channel on the CLKP and CLKN lanes.

Video data is output over the data lanes in high speed mode.

The data lanes enter low power mode during the horizontal

and vertical blanking periods.

The clock lanes are used to clock the output video. After the

ADV7281-M/ADV7281-MA are programmed, the clock lanes

exit low power mode and remain in high speed mode until the

part is reset or powered down.

The ADV7281-M/ADV7281-MA output video data in an 8-bit

YCrCb 4:2:2 format. The video data is output in an interlaced

format at a nominal data rate of 216 Mbps.

D0P

(1 BIT)

D0N

(1 BIT)

CLKP

(1 BIT)

CLKN

(1 BIT)

ITU-R BT.656

DATA

STREAM

CSI-2

VIDEO

DECODER

D-PHY

ANALOG

VIDEO

INPUT

CSI Tx DATA

OUTPUT (8 BITS)

DATA LANE LP

SIGNALS (2 BITS)

CLOCK LANE LP

SIGNALS (2 BITS)

Figure 15. MIPI CSI-2 Output Stage of the ADV7281-M/ADV7281-MA

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