ADV7281 datasheet(18/32 Pages) AD

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ADV7281

Data Sheet

Rev. A | Page 18 of 32

INPUT CONFIGURATION

The input format of the ADV7281-M/ADV7281-MA is

specified using the INSEL[4:0] bits (see Table 13). These bits

also configure the SDP core to process CVBS, differential

CVBS, Y/C (S-Video), or component (YPbPr) format. The

INSEL[4:0] bits are located in the user sub map of the register

space at Address 0x00[4:0]. For more information about the

registers, see the Register Maps section.

The INSEL[4:0] bits specify predefined analog input routing

schemes, eliminating the need for manual mux programming

and allowing the user to route the various video signal types

to the decoder. For example, if the CVBS input is selected, the

remaining channels are powered down.

Table 13. Input Format Specified by the INSEL[4:0] Bits

INSEL[4:0] Bit Value

Video Format

Analog Inputs

ADV7281

ADV7281-M

ADV7281-MA

00000

CVBS

CVBS input on AIN1

00001

CVBS

CVBS input on AIN2

00010

CVBS

Reserved

CVBS input on AIN3

00011

CVBS

Reserved

CVBS input on AIN4

00100

CVBS

Reserved

CVBS input on AIN5

00101

CVBS

Reserved

CVBS input on AIN6

00110

CVBS

CVBS input on AIN3

CVBS input on AIN5

CVBS input on AIN7

00111

CVBS

CVBS input on AIN4

CVBS input on AIN6

CVBS input on AIN8

01000

Y/C (S-Video)

Y input on AIN1;

C input on AIN2

Y input on AIN1;

C input on AIN2

Y input on AIN1;

C input on AIN2

01001

Y/C (S-Video)

Reserved

Y input on AIN3;

C input on AIN4

Y input on AIN3;

C input on AIN4

01010

Y/C (S-Video)

Reserved

Y input on AIN5;

C input on AIN6

01011

Y/C (S-Video)

Y input on AIN3;

C input on AIN4

Y input on AIN5;

C input on AIN6

Y input on AIN7;

C input on AIN8

01100

YPrPb

Reserved1

Y input on AIN1;

Pb input on AIN2;

Pr input on AIN3

Y input on AIN1;

Pb input on AIN2;

Pr input on AIN3

01101

YPrPb

Reserved1

Reserved

Y input on AIN4;

Pb input on AIN5;

Pr input on AIN6

01110

Differential CVBS

Positive input on AIN1;

Negative input on AIN2

Positive input on AIN1;

Negative input on AIN2

Positive input on AIN1;

Negative input on AIN2

01111

Differential CVBS

Reserved

Positive input on AIN3;

Negative input on AIN4

Positive input on AIN3;

Negative input on AIN4

10000

Differential CVBS

Reserved

Positive input on AIN5;

Negative input on AIN6

10001

Differential CVBS

Positive input on AIN3;

Negative input on AIN4

Positive input on AIN5;

Negative input on AIN6

Positive input on AIN7;

Negative input on AIN8

10010 to 11111

Reserved

Note that it is possible for the ADV7281 to receive YPbPr formats; however, a manual muxing scheme is required. In this case luma(Y) is fed in on AIN1 or AIN3, Blue

chroma(Pb) is fed in on AIN4 and red chroma (Pr) is fed in on AIN2.

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