ADV7281 datasheet(13/32 Pages) AD

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Data Sheet

ADV7281

Rev. A | Page 13 of 32

24 AIN5

23 AIN4

22 AIN3

21 AVDD

20 VREFN

19 VREFP

18 AIN2

17 AIN1

DGND

DVDDIO

DVDD

DGND

INTRQ

GPO2

GPO1

GPO0

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED TO DGND.

ADV7281-MA

TOP VIEW

(Not to Scale)

Figure 9. Pin Configuration, ADV7281-MA

Table 11. Pin Function Descriptions, ADV7281-MA

Pin No.

Mnemonic

Type

Description

1, 4

DGND

Ground

Ground for Digital Supply.

DVDDIO

Power

Digital I/O Power Supply (3.3 V).

DVDD

Power

Digital Power Supply (1.8 V).

INTRQ

Output

Interrupt Request Output. An interrupt occurs when certain signals are detected on the

input video.

6 to 8

GPO2 to

GPO0

Output

General-Purpose Outputs. These pins can be configured via I2C to allow control of external

devices.

D0P

Output

Positive MIPI Differential Data Output.

D0N

Output

Negative MIPI Differential Data Output.

CLKP

Output

Positive MIPI Differential Clock Output.

CLKN

Output

Negative MIPI Differential Clock Output.

MVDD

Power

MIPI Digital Power Supply (1.8 V).

XTALP

Output

Connect this pin to the external 28.63636 MHz crystal, or leave it unconnected if an external

1.8 V, 28.63636 MHz clock oscillator source is used to clock the ADV7281-MA. The crystal

used with the ADV7281-MA must be a fundamental crystal.

XTALN

Input

Input Pin for the External 28.63636 MHz Crystal. The crystal used with the ADV7281-MA

must be a fundamental crystal. If an external 1.8 V, 28.63636 MHz clock oscillator source

is used to clock the ADV7281-MA, the output of the oscillator is fed into the XTALN pin.

PVDD

Power

PLL Power Supply (1.8 V).

17, 18, 22,

23, 24, 25,

26, 27

AIN1 to AIN8

Input

Analog Video Input Channels.

VREFP

Output

Internal Voltage Reference Output.

VREFN

Output

Internal Voltage Reference Output.

AVDD

Power

Analog Power Supply (1.8 V).

RESET

Input

System Reset Input (Active Low). A minimum low reset pulse width of 5 ms is required to

reset the ADV7281-MA circuitry.

ALSB

Input

This pin selects the I2C write address for the ADV7281-MA. When ALSB is set to Logic 0, the

write address is 0x40; when ALSB is set to Logic 1, the write address is 0x42.

SDATA

Input/output

I2C Port Serial Data Input/Output.

SCLK

Input

I2C Port Serial Clock Input. The maximum clock rate is 400 kHz.

PWRDWN

Input

Power-Down Pin. A logic low on this pin places the ADV7281-MA in power-down mode.

EPAD (EP)

Exposed Pad. The exposed pad must be connected to DGND.

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