DP83840AVCE datasheet(28/91 Pages) TI1

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3.0 Functional Description (Continued)

National Semiconductor

Version A

3.5.5.2 Repeater Clock Distribution Example

The clock distribution within a multi-port repeater can be

designed in a variety of ways. Figure 12 provides a

simpliﬁed example of one possible timing distribution

scheme in a 100 Mb/s only repeater design. It should be

noted that in order to support Auto-Negotiation, a 20 MHz

reference would be required for each DP83840A device.

ENDEC

(DP83850

100RIC)

DP83840A (1)

DP83840A (2)

DP83840A (12)

DP83223

(1)

DP83223

(2)

DP83223

(12)

25 MHz

MHz

BUFFER

RX_CLK

MAC

PHY

PMD

RXD

TX_CLK

RX_CLK

TXD

MHz

FIGURE 12. Typical 100 Mb/s Repeater Clock Interconnection

FIGURE 11. Typical Adapter Clock and Data Typical

Due to the demanding timing constraints required to

maintain standards compliance, great care must be

taken in the design and layout of a multi-port repeater

system. The example provided in Figure 12 illustrates

interconnection only and should not be considered as a

reference design.

DP83840AVCE Datasheet(PDF) 28 Page - Texas Instruments

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