DP83840AVCE datasheet(63/91 Pages) TI1

63 / 91 page

6.0 Hardware User Information (Continued)

National Semiconductor

Version A

Symptoms:

An improper ﬁve bit PHY Address is latched into the

DP83840A upon power-on/reset.

Solution/Workaround:

In order to guarantee that a logic low level is latched-in to

PHYAD[3] upon power-up/reset, it is recommended that a

4.7k

Ω resistor be connected from this pin directly to

ground. Figure 23 illustrates the recommended connection

of external circuitry when using PHYAD[3] / SPEED_100 to

control

transistors

used

for

Common

Magnetics

implementations.

In order to guarantee that a logic high level is latched-in to

PHYAD[3] upon power-up/reset, it is recommended that a

1.0k

Ω resistor be connected from this pin directly to Vcc

and that a 1.2k

Ω resistor be connected in series between

this pin and the transistor control circuitry. It is important to

take note that the base resistor values (each 100

Ω in this

case) are lowered in order to compensate for the series

1.2k

Ω resistor with respect to proper transistor biasing.

Figure 24 illustrates the recommended connection of

external circuitry when using PHYAD[3] / SPEED_100 to

control

transistors

used

for

Common

Magnetics

implementations.

6.5 Collision De-Assertion Time

Problem:

In 100 Mb/s operation, the Collision De-Assertion time

violates the IEEE802.3u speciﬁcation.

Description:

The Collision De-Assertion time which is determined from

when TX_EN is deasserted to COL going low is speciﬁed

40ns

maximum

per

IEEE

802.3u/D5.3

section

22.2.4.1.9. This is a test mode function. The DP83840A

has a speciﬁcation of 87ns maximum.

TXREF

TXO+ Term

TXO- Term

PHYAD[3]/

SPEED_100

DP83840A

4.7k

Ω

1.2 k

Ω

1.2 k

Ω

1.2 k

Ω

GND

All resistors are 1/8th Watt, +/- 5% tolerance

Figure 23. Recommended Control Circuitry and Valid PHYAD[3] Logic Low Latch-in Value

Vcc

TXREF

TXO+ Term

TXO- Term

PHYAD[3]/

SPEED_100

DP83840A

1.0 k

Ω

All resistors are 1/8th Watt, +/- 5% tolerance

1.2k

Ω

100

Ω

100

Ω

100

Ω

Figure 24. Recommended Control Circuitry and Valid PHYAD[3] Logic High Latch-in Val

DP83840AVCE Datasheet(PDF) 63 Page - Texas Instruments

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