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DP83840AVCE Datasheet(PDF) 77 Page - Texas Instruments |
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DP83840AVCE Datasheet(HTML) 77 Page - Texas Instruments |
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77 / 91 page  8.0 Electrical Specifications (Continued) 76 Version A 8.5.2 100 Mb/s MII Receive Timing Note: RXD[3:0], RX_DV, and RX_ER are clocked out of the DP83840A on the falling edge of RX_CLK. However, in order to specify this parameter without the RX_CLK duty cycle affecting it, the timing is taken from the previous rising edge of RX_CLK. Parameter Description Notes Min Typ Max Units T1 RX_EN to RX_CLK, RXD[3:0], RX_ER, RX_DV Active All 100 Mb/s modes 0 20 ns T2 RX_EN to RX_CLK, RXD[3:0], RX_ER, RX_DV Tri-State All 100 Mb/s modes 0 30 ns T3 RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 100 Mb/s Translational mode (Normal) 10 30 ns RX_CLK to RXD[4:0], RX_DV, Delay 100 Mb/s Transparent mode (BP_4B5B) 10 30 ns RX_CLK to RXD[4:0], RX_DV, Delay 100 Mb/s Phaser mode (BP_ALIGN), Note 2 10 30 ns T4 RX_CLK Duty Cycle All 100 Mb/s modes 35 65 % RX_CLK RXD[3:0] RX_DV RX_ER Valid Data RX_EN T3 T1 T2 T4 |
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