DP83840AVCE datasheet(45/91 Pages) TI1

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4.0 Registers (Continued)

National Semiconductor

Version A

Isolate

(PHYAD = 00000),

ISOLATE:

1 = Isolates the DP83840A from the MII with the exception of the serial

management. When this bit is asserted, the DP83840A does not

respond to TXD[3:0], TX_EN, and TX_ER inputs, and it presents a

high impedance on its

TX_CLK, RX_CLK, RX_DV, RX_ER,

RXD[3:0], COL and CRS outputs. The CLK_25M output stays active

(if enabled) and the DP83840A still responds to serial management

transactions. During Isolate mode TX_EN has no effect, TD+/- will

transmit Idles, TXU+/- and TXS+/- will tri-state, transitions on the

receive inputs RD +/- and RXI +/- are ignored, and link is disabled.

0 =Normal Operation

If the PHY Address is set to 00000 the Isolate bit will be set upon power-

up/reset. Refer to section 3.2.4 for further detail.

Restart Auto-Ne-

gotiation

0, RW/SC

RESTART AUTO-NEGOTIATION:

1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation process.

If Auto-Negotiation is disabled (bit 12 of this register cleared), this bit

has no function. This bit is self-clearing and will return a value of 1

until Auto-Negotiation is initiated by the DP83840A, whereupon it will

self-clear. Operation of the Auto-Negotiation process is not affected

by the management entity clearing this bit.

0 = Normal Operation

Refer to section 3.9.4 for further detail.

Duplex Mode

1, RW

DUPLEX MODE:

1 = Full Duplex operation. Duplex selection is allowed when Auto-

Negotiation is disabled (bit 12 of this register is cleared). When Auto-

Negotiation is enabled, the duplex capability as specified in bits

[15:11] of the BMSR register (address 1h) reflect the current status.

This bit does not reflect duplex status.

0 = Half Duplex Operation

Collision Test

0, RW

COLLISION TEST:

1 = Collision Test enabled. When set, this bit will cause the COL signal

to be asserted in response to the assertion of TX_EN.

0 = Normal Operation

6:0

Reserved

X, RO

RESERVED: Write as 0, read as don't care.

4.3 BASIC MODE STATUS REGISTER (BMSR)

Address 01h

Bit

Bit Name

Default

Description

100BASE-T4

0, RO/P

100BASE-T4 CAPABLE:

1 = DP83840A able to perform in 100BASE-T4 mode

0 = DP83840A not able to perform in 100BASE-T4 mode

100BASE-TX Full

Duplex

1, RO/P

100BASE-TX FULL DUPLEX CAPABLE:

1 = DP83840A able to perform 100BASE-TX in full duplex mode

0 = DP83840A not able to perform 100BASE-TX in full duplex mode

100BASE-TX Half

Duplex

1, RO/P

100BASE-TX HALF DUPLEX CAPABLE:

1 = DP83840A able to perform 100BASE-TX in half duplex mode

0 = DP83840A not able to perform 100BASE-TX in half duplex mode

4.2 BASIC MODE CONTROL REGISTER (BMCR) (Continued)

Address 00h

Bit

Bit Name

Default

Description

DP83840AVCE Datasheet(PDF) 45 Page - Texas Instruments

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