DP83840AVCE datasheet(78/91 Pages) TI1

78 / 91 page

8.0 Electrical Specifications (Continued)

Version A

8.5.3 100 Mb/s Transmit Packet Timing

Parameter

Description

Notes

Min

Typ

Max

Units

TX_CLK to TD+/- Latency

100 Mb/s Translational mode (Normal)

3.0

bits

100 Mb/s Transparent mode (BP_4B5B)

3.0

bits

100 Mb/s Phaser mode (BP_ALIGN)

3.0

bits

TX_CLK

TX_EN

TXD

TD+/-

(J/K)

IDLE

DATA

8.5.4 100 Mb/s Transmit Packet Timing

Parameter

Description

Notes

Min

Typ

Max

Units

TX_CLK to TD+/- deassertion 100 Mb/s Translational mode (Normal)

100 Mb/s Transparent mode (BP_4B5B)

100 Mb/s Phaser mode (BP_ALIGN)

TX_CLK

TX_EN

TXD

TD+/-

(T/R)

DATA

IDLE

Note: Latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX_EN

to the first bit of the “j” code group as output from the TD+/- pins. 1 bit time = 10ns in 100 Mb/s mode

Note: De-assertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the de-assertion of TX_EN

to the first bit of the “T” code group as output from the TD+/- pins. 1 bit time = 10ns in 100 Mb/s mode

DP83840AVCE Datasheet(PDF) 78 Page - Texas Instruments

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