DP83840AVCE datasheet(47/91 Pages) TI1

47 / 91 page

4.0 Registers (Continued)

National Semiconductor

Version A

4.4 PHY IDENTIFIER REGISTER #1 (PHYIDR1)

Address 02h

The PHY Identiﬁer Registers #1 and #2 together form a unique identiﬁer for the DP83840A. The Identiﬁer consists of a

concatenation of the Organizationally Unique Identiﬁer (OUI), the vendor's model number and the model revision

number. A PHY may return a value of zero in each of the 32 bits of the PHY Identiﬁer if desired. The PHY Identiﬁer is

intended to support network management.

National Semiconductor's IEEE assigned OUI is 080017h.

4.5 PHY IDENTIFIER REGISTER #2 (PHYIDR2)

Address 03h

Extended Capa-

bility

1, RO/P

EXTENDED CAPABILITY:

1 = Extended register capable

0 = Basic register capable only

Bit

Bit Name

Default

Description

15:0

OUI_MSB

<00 1000 0000

0000 00>, RO/P

OUI MOST SIGNIFICANT BITS: This register stores bits 3 to 18 of the

OUI (080017h) to bits 15 to 0 of this register respectively. The most

significant two bits of the OUI are ignored (the IEEE standard refers to

these as bits 1 and 2).

Bit

Bit Name

Default

Description

15:10

OUI_LSB

<01 0111>, RO/P

OUI LEAST SIGNIFICANT BITS: Bits 19 to 24 of the OUI (080017h) are

mapped to bits 15 to 10 of this register respectively.

9:4

VNDR_MDL

<00 0000>, RO/P

VENDOR MODEL NUMBER: Six bits of vendor model number mapped

to bits 9 to 4 (most significant bit to bit 9).

3:0

MDL_REV

<0001>, RO/P

MODEL REVISION NUMBER: Four bits of vendor model revision

number mapped to bits 3 to 0 (most significant bit to bit 3). This field will

be incremented for all major DP83840A device changes.

4.3 BASIC MODE STATUS REGISTER (BMSR) (Continued)

Address 01h

Bit

Bit Name

Default

Description

DP83840AVCE Datasheet(PDF) 47 Page - Texas Instruments

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