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DP83840AVCE Datasheet(PDF) 74 Page - Texas Instruments |
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DP83840AVCE Datasheet(HTML) 74 Page - Texas Instruments |
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74 / 91 page  73 Version A 8.0 Electrical Specifications 8.3 CLOCK TIMING 8.3.1 Clock Reference and Clock Generation Timing Parameter Description Notes Min Typ Max Units T1 OSCIN to CLK25M Delay OSCIN = 50 MHz 0 30 40 ns T2 CLK25M Rise Time 10% to 90% 5 ns T3 CLK25M Fall Time 90% to 10% 5 ns T4 OSCIN to TX_CLK Delay 10 Mb/s Operation (MII Nibble Mode) 10 ns T4a OSCIN to TX_CLK Delay 10 Mb/s Operation (MII Serial Mode) 10 ns T5 REFIN to TX_CLK Delay 100 Mb/s Operation -3.0 +3.0 ns T6 TX_CLK Duty Cycle 10 Mb/s Nibble (2.5 MHz), 10 Mb/s Serial (10 MHz) 100 Mb/s Nibble (25 MHz) 35 65 % OSCIN CLK25M REFIN TX_CLK T1 T5 T1 T4 T2 T3 T6 |
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