DP83840AVCE datasheet(65/91 Pages) TI1

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6.0 Hardware User Information (Continued)

National Semiconductor

Version A

Symptoms:

National believes that there will be no system ramiﬁcation

due to the DP83840A not meeting the IEEE speciﬁcation

for return loss. National Semiconductor has done extensive

system testing with DP83840A’s that have return loss in

the range of 4-6dB, and did not see any degradation in

system performance.

Solution/Workaround:

To improve the return loss at idle, National Semiconductor

recommends that 1000pF capacitors be place in parallel to

the 10.5

Ω termination resistors connected to the TXU+/-

pins. Figure 26 illustrates the recommended connection of

external components to improve return loss.

6.9 Low Power Mode

Problem:

The DP83840A sometimes fails to Auto-Negotiate when

switching from 100 Mb/s link partner to a 10 Mb/s link

partner when the low power pin (pin 2) is driven by

Speed_100/PhyAdr<3> (pin 89).

The low power mode works when used in a 100 Mb/s only

operation.

Description:

Any application using the DP83840A (with the low power

pin driven by the Speed_100 pin) will sometimes fail to

Auto-Negotiate to the 10 Mb/s link partner that has ﬁrst

established a link with a 100 Mb/s link partner and then is

disconnected from the 100 Mb/s link partner and then

connected to a 10 Mb/s link partner. The reason for this is

that in 100 Mb/s mode, the part will be conﬁgured for low

power mode and shut down the 10 Mb/s and Auto-

Negotiation circuitry in the DP83840A and when it tries to

connect to a 10 Mb/s link partner the 10 Mb/s and Auto-

Negotiation circuitry might not be fully powered up.

Symptoms:

When this problem occurs, no link will be established with

the 10 Mb/s link partner and the FLP signal being sent by

the DP83840A will be half it’s normal amplitude. This

indicates that the 10 Mb/s section of the chip has not

powered up properly.

Solution/Workaround:

It is recommended that in 10/100 application that the low

power mode of the device not be used.

In 100 Mb/s only applications, it is recommended that the

low power pin be pulled high through a 4.7k

Ω resister.

6.10 Software Reset

Problem:

Hardware Conﬁguration pins require a (4.7k

Ω or less) pull

up/down resistor to insure that the Physical Address is

stable at latching time.

Description:

The following is an explanation of events based on

software reset:

1. First high byte is written via MDIO

2. Software reset is true for the next 500ns.

3. At synchronous de-assertion of the reset all mode pins

and Phy Address pins are latched.

4. Output enables for Phy Address pins are disabled (they

will become inputs) from start of the reset to 1700ns after

reset assertion.

5. Within 250ns from assertion of software reset, the phy

address has to be stable. This implies that the RC time

constant should be faster than 250ns so that Phy address

will be latched correctly with reset synchronous de-

assertion.

6. DP83840A Phy Address pin drivers have been modiﬁed

to provide more drive current than the DP83840. This will

increase the capacitance at the pin, hence the resistance

will need to be reduced accordingly to keep the time

constant low.

DP83840A

Pin 25 (TXU-)

Pin 24 (TXU+)

RJ45

1:2

10.5

Ω

10.5

Ω

1000pF

Figure 26. Recommended External Circuitry to Improve Transmit Return Loss

DP83840AVCE Datasheet(PDF) 65 Page - Texas Instruments

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