AS3911 datasheet(124/149 Pages) AMSCO

124 / 149 page

AS3911 – 124

ams Datasheet, Confidential: 2013-Oct [2-03]

A p pl i c at io n I n f o r m at i o n

Figure 117:

Flowchart for ISO14443A Anticollision with AS3911

1) Fill fifo with

SELn + NVB (0x20)

2)Set Register:

Number of transmitted bytes

1) Send Command:

Transmit without CRC

2) Following interrupts:

I_dct

I_txe

I_col (if collision occurs)

I_rxs

I_rxe

FIFO is filled in with PICC response

I_col ?

1) Read Collision Display

much is the valid data

before the collison

occured,

2) Read FIFO for the

response from PICC

Yes

Read out FIFO for the valid

data from the selected PICC

1) Fill FIFO with part 1 of bit

collision anticollision:

SELn + NVB (available from

valid tag response) +

received valid data +1 or 0

for the bit where the collision

occured

2) Set Register:

Mention the number of

received full bytes and split

bits + 1 bit in:

Number of transmitted bytes

Number of full bytes

Number of transmitted bytes

FIFO is filled in with PICC response

Set:

no_CRC_rx = 0,

antcl = 0

PICC sends complete UID

Cascade level n

(n =1)

Send SELECT:

Fill FIFO with

SELn + NVB(0x70) + UID CLn

1) Send Command:

Transmit with CRC

2) Following interrupts:

I_dct

I_txe

I_rxe

FIFO is filled with SAK

UID complete?

End Anticollision with

RATS

Enter Cascade Level n+1

Yes

SELn=0x93 for n=1 for 4 bytes UID

SELn=0x95 for n=2 for 7 bytes UID

SELn=0x97 for n=3 for 10 bytes UID

Set:

no_CRC_rx = 1,

antcl = 1

NOTE: Since SPI is byte oriented, in

case of SPLIT BYTE scenario, the invalid

MSB bits must be ignored when

reading out the FIFO for the received

data. Similarly, 0s must be

concatenated As MSB bits to complete

a byte for the Transmit (which will then

be ignored based on register 0x1E)

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