AS3911 datasheet(130/149 Pages) AMSCO

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AS3911 – 130

ams Datasheet, Confidential: 2013-Oct [2-03]

A p pl i c at io n I n f o r m at i o n

Sequence loops through point 2. In case the last initiator

command is sent in next sequence (DLS_REQ in case of

NFCIP-1 protocol) the bit nfc_ar in the Mode Definition

initiator field after the target has switched of its field.

NFCIP-1 Active Communication Target

The AS3911 target mode is activated by setting bit targ in the

Mode Definition Register to 1. When target mode is activated

the External Field Detector is automatically enabled by setting

bit en_fd in the Auxiliary Definition Register.

When bit targ is set and all bits of the Operation Control Register

are set to 0, the AS3911 is in low power Initial NFC Target Mode.

In this mode the External Field Detector with Peer Detection

Threshold is enabled.

There are two different NFC target modes implemented

(defined by mode bits of the Mode Definition Register): the bit

rate detection mode and normal mode. In the bit rate detection

mode the framing logic performs automatic detection of the

initiator data rate and writes it in the NFCIP Bit Rate Detection

Display Register. In the normal mode it is supposed that the

data rate defined in the Bit Rate Definition Register is used.

After selecting the NFCIP-1 active target mode the Receiver and

Transmitter have to be configured properly. Configuration is the

same as in case of NFCIP-1 active initiator mode. This

configuration can be done automatically by sending direct

command Analog Preset (see “Analog Preset” on page 53).

NFCIP-1 active communication sequence when bit nfc_ar in the

Mode Definition Register is set (automatic Response RF

Collision Avoidance sequence). During this sequence bits

nfc_n1 and nfc_n0 of the Auxiliary Definition Register have to

be 0 to produce Response Collision Avoidance with n=0.

The following sequence assumes that the AS3911 is in the low

power Initial NFC Target Mode with the bit rate detection mode

selected. Bit nfc_ar in the Mode Definition Register is set

(automatic Response RF Collision Avoidance sequence). When

the initiator field is detected the following sequence is

executed:

An IRQ with I_eon flag set is sent to the controller.

The controller turns on the oscillator, regulator and

receiver. Mask-receive Timer is started by sending direct

command Start Mask-receive Timer. After the Mask

Receive Timer expires the receiver output starts to be

observed to detect start of the initiator message.

Once the start of initiator message is detected, an IRQ

due to start of receive is sent, the framing logic switches

on a module which automatically recognizes the bit rate

of signal sent by the initiator. Once the bit rate is

recognized an IRQ with I_nfct flag set is sent and the bit

rate is automatically loaded in the NFCIP Bit Rate

Detection Display Register. Detection of bit rate is also

a condition that automatic Response RF Collision

AS3911 Datasheet(PDF) 130 Page - ams AG

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