EP1C3 datasheet(32/385 Pages) ETC2

32 / 385 page

2–12

Altera Corporation

Preliminary

May 2008

Cyclone Device Handbook, Volume 1

The Quartus II Compiler automatically creates carry chain logic during

design processing, or you can create it manually during design entry.

Parameterized functions such as LPM functions automatically take

advantage of carry chains for the appropriate functions.

The Quartus II Compiler creates carry chains longer than 10 LEs by

linking LABs together automatically. For enhanced fitting, a long carry

chain runs vertically allowing fast horizontal connections to M4K

memory blocks. A carry chain can continue as far as a full column.

Clear and Preset Logic Control

LAB-wide signals control the logic for the register's clear and preset

signals. The LE directly supports an asynchronous clear and preset

function. The register preset is achieved through the asynchronous load

of a logic high. The direct asynchronous preset does not require a

NOT-gate push-back technique. Cyclone devices support simultaneous

preset/ asynchronous load and clear signals. An asynchronous clear

signal takes precedence if both signals are asserted simultaneously. Each

LAB supports up to two clears and one preset signal.

In addition to the clear and preset ports, Cyclone devices provide a

chip-wide reset pin (

DEV_CLRn) that resets all registers in the device. An

option set before compilation in the Quartus II software controls this pin.

This chip-wide reset overrides all other control signals.

MultiTrack

Interconnect

In the Cyclone architecture, connections between LEs, M4K memory

blocks, and device I/O pins are provided by the MultiTrack interconnect

structure with DirectDriveTM technology. The MultiTrack interconnect

consists of continuous, performance-optimized routing lines of different

speeds used for inter- and intra-design block connectivity. The Quartus II

Compiler automatically places critical design paths on faster

interconnects to improve design performance.

DirectDrive technology is a deterministic routing technology that ensures

identical routing resource usage for any function regardless of placement

within the device. The MultiTrack interconnect and DirectDrive

technology simplify the integration stage of block-based designing by

eliminating the re-optimization cycles that typically follow design

changes and additions.

The MultiTrack interconnect consists of row and column interconnects

that span fixed distances. A routing structure with fixed length resources

for all devices allows predictable and repeatable performance when

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