EP1C3 datasheet(53/385 Pages) ETC2

53 / 385 page

Altera Corporation

2–33

May 2008

Preliminary

Global Clock Network and Phase-Locked Loops

Table 2–6 shows the PLL features in Cyclone devices. Figure 2–25 shows

a Cyclone PLL.

Figure 2–25. Cyclone PLL

Note (1)

Notes to Figure 2–25:

(1)

The EP1C3 device in the 100-pin TQFP package does not support external outputs or LVDS inputs. The EP1C6

device in the 144-pin TQFP package does not support external output from PLL2.

(2)

LVDS input is supported via the secondary function of the dedicated clock pins. For PLL 1, the

CLK0 pin’s secondary

function is

LVDSCLK1p and the CLK1 pin’s secondary function is LVDSCLK1n. For PLL 2, the CLK2 pin’s secondary

function is

LVDSCLK2p and the CLK3 pin’s secondary function is LVDSCLK2n.

(3)

PFD: phase frequency detector.

Table 2–6. Cyclone PLL Features

Feature

PLL Support

Clock multiplication and division

m/(n × post-scale counter) (1)

Phase shift

Down to 125-ps increments (2), (3)

Programmable duty cycle

Yes

Number of internal clock outputs

Number of external clock outputs

One differential or one single-ended (4)

Notes to Table 2–6:

(1)

The m counter ranges from 2 to 32. The n counter and the post-scale counters

range from 1 to 32.

(2)

The smallest phase shift is determined by the voltage-controlled oscillator (VCO)

period divided by 8.

(3)

For degree increments, Cyclone devices can shift all output frequencies in

increments of 45°. Smaller degree increments are possible depending on the

frequency and divide parameters.

(4)

The EP1C3 device in the 100-pin TQFP package does not support external clock

output. The EP1C6 device in the 144-pin TQFP package does not support external

clock output from PLL2.

Charge

Pump

VCO

PFD (3)

Loop

Filter

CLK0 or

LVDSCLK1p (2)

CLK1 or

LVDSCLK1n (2)

÷n

÷m

Δt

Global clock

I/O buffer

÷g0

÷g1

÷e

VCO Phase Selection

Selectable at Each PLL

Output Port

Post-Scale

Counters

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