EP1C3 datasheet(77/385 Pages) ETC2

77 / 385 page

Altera Corporation

3–1

May 2008

Preliminary

3. Configuration and Testing

IEEE Std. 1149.1

(JTAG) Boundary

Scan Support

All Cyclone® devices provide JTAG BST circuitry that complies with the

IEEE Std. 1149.1a-1990 specification. JTAG boundary-scan testing can be

performed either before or after, but not during configuration. Cyclone

devices can also use the JTAG port for configuration together with either

the Quartus® II software or hardware using either Jam Files (.jam) or Jam

Byte-Code Files (.jbc).

Cyclone devices support reconfiguring the I/O standard settings on the

IOE through the JTAG BST chain. The JTAG chain can update the I/O

standard for all input and output pins any time before or during user

mode. Designers can use this ability for JTAG testing before configuration

when some of the Cyclone pins drive or receive from other devices on the

board using voltage-referenced standards. Since the Cyclone device

might not be configured before JTAG testing, the I/O pins might not be

configured for appropriate electrical standards for chip-to-chip

communication. Programming those I/O standards via JTAG allows

designers to fully test I/O connection to other devices.

The JTAG pins support 1.5-V/1.8-V or 2.5-V/3.3-V I/O standards. The

TDO pin voltage is determined by the VCCIO of the bank where it resides.

The bank VCCIO selects whether the JTAG inputs are 1.5-V, 1.8-V, 2.5-V, or

3.3-V compatible.

Cyclone devices also use the JTAG port to monitor the operation of the

device with the SignalTap® II embedded logic analyzer. Cyclone devices

support the JTAG instructions shown in Table 3–1.

Table 3–1. Cyclone JTAG Instructions (Part 1 of 2)

JTAG Instruction

Instruction Code

Description

SAMPLE/PRELOAD

00 0000 0101

Allows a snapshot of signals at the device pins to be captured and

examined during normal device operation, and permits an initial

data pattern to be output at the device pins. Also used by the

SignalTap II embedded logic analyzer.

EXTEST (1)

00 0000 0000

Allows the external circuitry and board-level interconnects to be

tested by forcing a test pattern at the output pins and capturing test

results at the input pins.

BYPASS

11 1111 1111

Places the 1-bit bypass register between the TDI and TDO pins,

which allows the BST data to pass synchronously through selected

devices to adjacent devices during normal device operation.

C51003-1.4

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