EP1C3 datasheet(45/385 Pages) ETC2

45 / 385 page

Altera Corporation

2–25

May 2008

Preliminary

Embedded Memory

Independent Clock Mode

The M4K memory blocks implement independent clock mode for true

dual-port memory. In this mode, a separate clock is available for each port

(ports A and B). Clock A controls all registers on the port A side, while

clock B controls all registers on the port B side. Each port, A and B, also

supports independent clock enables and asynchronous clear signals for

port A and B registers. Figure 2–17 shows an M4K memory block in

independent clock mode.

Figure 2–17. Independent Clock Mode

Notes (1), (2)

Notes to Figure 2–17:

(1)

All registers shown have asynchronous clear ports.

(2)

Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both

read and write operations.

Input/Output Clock Mode

Input/output clock mode can be implemented for both the true and

simple dual-port memory modes. On each of the two ports, A or B, one

clock controls all registers for inputs into the memory block: data input,

wren, and address. The other clock controls the block's data output

registers. Each memory block port, A or B, also supports independent

clock enables and asynchronous clear signals for input and output

registers. Figures 2–18 and 2–19 show the memory block in input/output

clock mode.

ENA

data

A[ ]

address

A[ ]

Memory Block

256 ´ 16 (2)

512 ´ 8

1,024 ´ 4

2,048 ´ 2

4,096 ´ 1

Data In

Address A

Write/Read

Enable

Data Out

Data In

Address B

Write/Read

Enable

Data Out

clken

clock

ENA

wren

6 LAB Row Clocks

A[ ]

data

B[ ]

address

B[ ]

clken

clock

wren

B[ ]

ENA

byteena

A[ ]

Byte Enable A

Byte Enable B

byteena

B[ ]

ENA

Write

Pulse

Generator

Write

Pulse

Generator

EP1C3 Datasheet(PDF) 45 Page - List of Unclassifed Manufacturers

EP1C3 Datasheet(HTML) 45 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL