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EP1C3 Datasheet(PDF) 41 Page - List of Unclassifed Manufacturers

Part # EP1C3
Description  Cyclone Device Handbook, Volume 1
PDF  385 Pages
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Manufacturer  ETC2 [List of Unclassifed Manufacturers]
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EP1C3 Datasheet(HTML) 41 Page - List of Unclassifed Manufacturers

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Altera Corporation
2–21
May 2008
Preliminary
Embedded Memory
register outputs (number of taps n × width w) must be less than the
maximum data width of the M4K RAM block (×36). To create larger shift
registers, multiple memory blocks are cascaded together.
Data is written into each address location at the falling edge of the clock
and read from the address at the rising edge of the clock. The shift register
mode logic automatically controls the positive and negative edge
clocking to shift the data in one clock cycle. Figure 2–14 shows the M4K
memory block in the shift register mode.
Figure 2–14. Shift Register Memory Configuration
Memory Configuration Sizes
The memory address depths and output widths can be configured as
4,096 × 1, 2,048 × 2, 1,024 × 4, 512 × 8 (or 512 × 9 bits), 256 × 16 (or 256 × 18
bits), and 128 × 32 (or 128 × 36 bits). The 128 × 32- or 36-bit configuration
m-Bit Shift Register
w
w
m-Bit Shift Register
m-Bit Shift Register
m-Bit Shift Register
w
w
w
w
w
w
w
× m × n Shift Register
n Number
of Taps



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