EP1C3 datasheet(43/385 Pages) ETC2

43 / 385 page

Altera Corporation

2–23

May 2008

Preliminary

Embedded Memory

Byte Enables

M4K blocks support byte writes when the write port has a data width of

16, 18, 32, or 36 bits. The byte enables allow the input data to be masked

so the device can write to specific bytes. The unwritten bytes retain the

previous written value. Table 2–5 summarizes the byte selection.

Control Signals and M4K Interface

The M4K blocks allow for different clocks on their inputs and outputs.

Either of the two clocks feeding the block can clock M4K block registers

(

renwe, address, byte enable, datain, and output registers). Only the

output register can be bypassed. The six

labclk signals or local

interconnects can drive the control signals for the A and B ports of the

M4K block. LEs can also control the

clock_a, clock_b, renwe_a,

renwe_b, clr_a, clr_b, clocken_a, and clocken_b signals, as

shown in Figure 2–15.

The R4, C4, and direct link interconnects from adjacent LABs drive the

M4K block local interconnect. The M4K blocks can communicate with

LABs on either the left or right side through these row resources or with

LAB columns on either the right or left with the column resources. Up to

10 direct link input connections to the M4K block are possible from the

left adjacent LABs and another 10 possible from the right adjacent LAB.

M4K block outputs can also connect to left and right LABs through 10

direct link interconnects each. Figure 2–16 shows the M4K block to logic

array interface.

Table 2–5. Byte Enable for M4K Blocks

Notes (1), (2)

byteena[3..0]

datain ×18

datain ×36

[0] = 1

[8..0]

[1] = 1

[17..9]

[2] = 1

—

[26..18]

[3] = 1

—

[35..27]

Notes to Table 2–5:

(1)

Any combination of byte enables is possible.

(2)

Byte enables can be used in the same manner with 8-bit words, i.e., in ×16 and ×32

modes.

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