EP1C3 datasheet(4/385 Pages) ETC2

4 / 385 page

Altera Corporation

Preliminary

Cyclone Device Handbook, Volume 1

Dual-Purpose Clock Pins .............................................................................................................. 2–31

Combined Resources ..................................................................................................................... 2–31

PLLs .................................................................................................................................................. 2–32

Clock Multiplication and Division .............................................................................................. 2–35

External Clock Inputs .................................................................................................................... 2–36

External Clock Outputs ................................................................................................................. 2–36

Clock Feedback ............................................................................................................................... 2–37

Phase Shifting ................................................................................................................................. 2–37

Lock Detect Signal .......................................................................................................................... 2–37

Programmable Duty Cycle ........................................................................................................... 2–38

Control Signals ................................................................................................................................ 2–38

I/O Structure ........................................................................................................................................ 2–39

External RAM Interfacing ............................................................................................................. 2–46

DDR SDRAM and FCRAM ........................................................................................................... 2–46

Programmable Drive Strength .....................................................................................................2–49

Open-Drain Output ........................................................................................................................ 2–50

Slew-Rate Control .......................................................................................................................... 2–51

Bus Hold .......................................................................................................................................... 2–51

Programmable Pull-Up Resistor .................................................................................................. 2–51

Advanced I/O Standard Support ................................................................................................ 2–52

LVDS I/O Pins ................................................................................................................................ 2–54

MultiVolt I/O Interface ................................................................................................................. 2–54

Power Sequencing and Hot Socketing ............................................................................................. 2–55

Referenced Documents ....................................................................................................................... 2–56

Document Revision History ............................................................................................................... 2–56

Chapter 3. Configuration and Testing

IEEE Std. 1149.1 (JTAG) Boundary Scan Support ............................................................................. 3–1

SignalTap II Embedded Logic Analyzer ............................................................................................ 3–5

Configuration ......................................................................................................................................... 3–5

Operating Modes .............................................................................................................................. 3–6

Configuration Schemes ................................................................................................................... 3–6

Referenced Documents ......................................................................................................................... 3–7

Document Revision History ................................................................................................................. 3–7

Chapter 4. DC and Switching Characteristics

Operating Conditions ........................................................................................................................... 4–1

Power Consumption ............................................................................................................................. 4–8

Timing Model ......................................................................................................................................... 4–9

Preliminary and Final Timing ........................................................................................................ 4–9

Performance .................................................................................................................................... 4–10

Internal Timing Parameters .......................................................................................................... 4–11

External Timing Parameters ......................................................................................................... 4–15

External I/O Delay Parameters .................................................................................................... 4–21

Maximum Input and Output Clock Rates .................................................................................. 4–27

PLL Timing ...................................................................................................................................... 4–29

Referenced Document ......................................................................................................................... 4–31

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