EP1C3 datasheet(5/385 Pages) ETC2

5 / 385 page

Altera Corporation

Preliminary

Contents

Document Revision History ............................................................................................................... 4–31

Chapter 5. Reference and Ordering Information

Software .................................................................................................................................................. 5–1

Device Pin-Outs ..................................................................................................................................... 5–1

Ordering Information ........................................................................................................................... 5–1

Referenced Documents ......................................................................................................................... 5–2

Document Revision History ................................................................................................................. 5–2

Section II. Clock Management

Revision History .................................................................................................................................... 5–1

Chapter 6. Using PLLs in Cyclone Devices

Introduction ............................................................................................................................................ 6–1

Hardware Overview ........................................................................................................................ 6–1

Software Overview .......................................................................................................................... 6–4

Pins and Clock Network Connections .......................................................................................... 6–6

Hardware Features ................................................................................................................................ 6–8

Clock Multiplication and Division ................................................................................................ 6–8

Phase Shifting ................................................................................................................................... 6–9

Programmable Duty Cycle ........................................................................................................... 6–10

External Clock Output ................................................................................................................... 6–11

Control Signals ................................................................................................................................ 6–12

Clock Feedback Modes ....................................................................................................................... 6–13

Normal Mode .................................................................................................................................. 6–14

Zero Delay Buffer Mode ................................................................................................................ 6–15

No Compensation .......................................................................................................................... 6–15

Pins ......................................................................................................................................................... 6–16

Board Layout ........................................................................................................................................ 6–17

VCCA and GNDA .......................................................................................................................... 6–17

Jitter Considerations ...................................................................................................................... 6–19

Specifications ........................................................................................................................................ 6–20

Software Support ................................................................................................................................. 6–20

Quartus II altpll Megafunction ..................................................................................................... 6–20

altpll Input Ports ............................................................................................................................. 6–22

altpll Output Ports ......................................................................................................................... 6–23

MegaWizard Customization ......................................................................................................... 6–23

MegaWizard Page Description .....................................................................................................6–25

Compilation Report ....................................................................................................................... 6–31

Timing Analysis .............................................................................................................................. 6–33

Simulation ....................................................................................................................................... 6–37

Global Clock Network ........................................................................................................................ 6–38

Dedicated Clock Input Pins .......................................................................................................... 6–40

Dual-Purpose Clock I/O Pins ...................................................................................................... 6–40

Combined Sources .......................................................................................................................... 6–41

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