EP1C3 datasheet(57/385 Pages) ETC2

57 / 385 page

Altera Corporation

2–37

May 2008

Preliminary

Global Clock Network and Phase-Locked Loops

does not have dedicated clock output pins. The EP1C6 device in the

144-pin TQFP package only supports dedicated clock outputs from

PLL 1.

Clock Feedback

Cyclone PLLs have three modes for multiplication and/or phase shifting:

■

Zero delay buffer mode

⎯The external clock output pin is phase-

aligned with the clock input pin for zero delay.

■

Normal mode

⎯If the design uses an internal PLL clock output, the

normal mode compensates for the internal clock delay from the input

clock pin to the IOE registers. The external clock output pin is phase

shifted with respect to the clock input pin if connected in this mode.

You defines which internal clock output from the PLL should be

phase-aligned to compensate for internal clock delay.

■

No compensation mode

⎯In this mode, the PLL will not compensate

for any clock networks.

Phase Shifting

Cyclone PLLs have an advanced clock shift capability that enables

programmable phase shifts. You can enter a phase shift (in degrees or

time units) for each PLL clock output port or for all outputs together in

one shift. You can perform phase shifting in time units with a resolution

range of 125 to 250 ps. The finest resolution equals one eighth of the VCO

period. The VCO period is a function of the frequency input and the

multiplication and division factors. Each clock output counter can choose

a different phase of the VCO period from up to eight taps. You can use this

clock output counter along with an initial setting on the post-scale

counter to achieve a phase-shift range for the entire period of the output

clock. The phase tap feedback to the m counter can shift all outputs to a

single phase. The Quartus II software automatically sets the phase taps

and counter settings according to the phase shift entered.

Lock Detect Signal

The lock output indicates that there is a stable clock output signal in

phase with the reference clock. Without any additional circuitry, the lock

signal may toggle as the PLL begins tracking the reference clock.

Therefore, you may need to gate the lock signal for use as a

system-control signal. For correct operation of the lock circuit below

–20 C, fIN/N > 200 MHz.

EP1C3 Datasheet(PDF) 57 Page - List of Unclassifed Manufacturers

EP1C3 Datasheet(HTML) 57 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL