EP1C3 datasheet(74/385 Pages) ETC2

74 / 385 page

2–54

Altera Corporation

Preliminary

May 2008

Cyclone Device Handbook, Volume 1

Each I/O bank can support multiple standards with the same VCCIO for

input and output pins. For example, when VCCIO is 3.3-V, a bank can

support LVTTL, LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs.

LVDS I/O Pins

A subset of pins in all four I/O banks supports LVDS interfacing. These

dual-purpose LVDS pins require an external-resistor network at the

transmitter channels in addition to 100-

Ω termination resistors on

receiver channels. These pins do not contain dedicated serialization or

deserialization circuitry; therefore, internal logic performs serialization

and deserialization functions.

Table 2–13 shows the total number of supported LVDS channels per

device density.

MultiVolt I/O Interface

The Cyclone architecture supports the MultiVolt I/O interface feature,

which allows Cyclone devices in all packages to interface with systems of

different supply voltages. The devices have one set of VCC pins for

internal operation and input buffers (VCCINT), and four sets for I/O

output drivers (VCCIO).

Table 2–13. Cyclone Device LVDS Channels

Device

Pin Count

Number of LVDS Channels

EP1C3

100

(1)

144

EP1C4

324

103

400

129

EP1C6

144

240

256

EP1C12

240

256

324

103

EP1C20

324

400

129

Note to Table 2–13:

(1)

EP1C3 devices in the 100-pin TQFP package do not support the LVDS I/O

standard.

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