B3-9

EM78P156E

VI.3 TCC/WDT & Prescaler

There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available for the TCC only

or the WDT only at the same time and the PAB bit of the CONT register is used to determine the prescaler assigment.

The PSR0~PSR2 bits determine the ratio. The prescaler will be cleared by the instructions which write to TCC each time,

when assigned to TCC mode. The WDT and prescaler, when assigned to WDT mode, will be cleared by the “WDTC”

and “SLEP” instructions. Fig.5 depicts the circuit diagram of TCC/WDT.

•

R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be internal clock or external clock input (edge

selectable from TCC pin). If TCC signal source is from internal clock, TCC will increase by 1 in every instruction

cycle (without prescaler). Refer to Fig.5, CLK=Fosc/2 or CLK=Fosc/4 is depended on the CODE option bit CLKS.

CLK=Fosc/2 if CLKS bit is “0”, and CLK=Fosc/4 if CLKS bit is “1”. If TCC signal source is from external clock

input, TCC will increase by 1 on every falling edge or rising edge of TCC pin.

•

The watchdog timer is a free running on-chip RC oscillator. The WDT will keep running even the oscillator driver

has been turned off (i.e. in sleep mode). During the normal operation or the sleep mode, a WDT time-out (if enabled)

will cause the device to reset. The WDT can be enabled or disabled at any time during the normal mode by software

programming. Refer to WDTE bit of IOCE register. With no presacler, the WDT time-out period is approximately

18 ms.

Fig. 5 Block diagram of TCC and WDT

Data Bus

8-bit Counter

8-to-1 MUX

TCC overflow interrupt

PSR0 ~PSR2

WDT time-out

WDTE

(in IOCE)

TCC

Pin

TE

PAB

MUX

TS

PAB

PAB

1

0

0

1

1

0

CLK(Fosc/2 or Fosc/4)

TCC(R1)

M

U

X

M

U

X

1

0

M

U

X

SYNC

2 cycles

WDT

IOCA

VI.4 I/O Ports

The I/O registers, both Port 5 and Port 6, are bi-directional tri-state I/O ports. Port 6 can be pulled high internally

by software. In addition, Port 6 can also have open-drain output by software. There is an input status changed interrupt

(or wake-up) function on Port 6. P50 ~ P52 and P60 ~ P63 pins can be pulled down by software. Each I/O pin can be

defined as “input” or “output” pin by the I/O control registers (IOC5 ~ IOC6). P50~P51 are the R-option pins enabled

by setting the ROC bit in the IOCE register to 1. While the R-option function is used, P50~P51 are recommended to be

used as output pins. During the period of R-option being enabled, P50~P51 must be programmed as input pins. In the

R-option mode, the current consuming by the Rex should be taken into the consideration, if the low power consumption

is concerned.