82371AB datasheet(97/284 Pages) INTEL

97 / 284 page

82371AB (PIIX4)

4/9/97 2:23 PM PIIX4aDS

INTEL CONFIDENTIAL

(until publication date)

PRELIMINARY

Bit

Description

15:14

Reserved.

13:12

Secondary Drive 1 Cycle Time (SCT1). These bit settings determine the minimum data write strobe

Cycle Time (CT) and minimum Ready to Pause time (RP).

Bits[13:12]

Time

CT=4 PCICLK, RP=6 PCICLK

CT=3 PCICLK, RP=5 PCICLK

CT=2 PCICLK, RP=4 PCICLK

Reserved

11:10

Reserved.

9:8

Secondary Drive 0 Cycle Time (SCT0). These bit settings determine the minimum data write strobe

Cycle Time (CT) and minimum Ready to Pause time (RP).

Bits[13:12]

Time

CT=4 PCICLK, RP=6 PCICLK

CT=3 PCICLK, RP=5 PCICLK

CT=2 PCICLK, RP=4 PCICLK

Reserved

7:6

Reserved.

5:4

Primary Drive 1 Cycle Time (PCT1). These bit settings determine the minimum data write strobe

Cycle Time (CT) and minimum Ready to Pause time (RP).

Bits[13:12]

Time

CT=4 PCICLK, RP=6 PCICLK

CT=3 PCICLK, RP=5 PCICLK

CT=2 PCICLK, RP=4 PCICLK

Reserved

3:2

Reserved.

1:0

Primary Drive 0 Cycle Time (PCT0). These bit settings determine the minimum data write strobe

Cycle Time (CT) and minimum Ready to Pause time (RP).

Bits[13:12]

Time

CT=4 PCICLK, RP=6 PCICLK

CT=3 PCICLK, RP=5 PCICLK

CT=2 PCICLK, RP=4 PCICLK

Reserved

82371AB Datasheet(PDF) 97 Page - Intel Corporation

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