82371AB datasheet(13/284 Pages) INTEL

13 / 284 page

82371AB (PIIX4)

4/9/97 2:23 PM PIIX4aDS

INTEL CONFIDENTIAL

(until publication date)

PRELIMINARY

PIIX4 can be configured for a full ISA bus or a subset of the ISA bus called the Extended IO (EIO) bus. The use

of the EIO bus allows unused signals to be configured as general purpose inputs and outputs. PIIX4 can directly

drive up to five ISA slots without external data or address buffering. It also provides byte-swap logic, I/O

recovery support, wait-state generation, and SYSCLK generation. X-Bus chip selects are provided for Keyboard

Controller, BIOS, Real Time Clock, a second microcontroller, as well as two programmable chip selects.

PIIX4 can be configured as either a subtractive decode PCI to ISA bridge or as a positive decode bridge. This

gives a system designer the option of placing another subtractive decode bridge in the system (e.g., an Intel

380FB Dock Set).

IDE Interface (Bus Master capability and synchronous DMA Mode)

The fast IDE interface supports up to four IDE devices providing an interface for IDE hard disks and CD ROMs.

Each IDE device can have independent timings. The IDE interface supports PIO IDE transfers up to 14

Mbytes/sec and Bus Master IDE transfers up to 33 Mbytes/sec. It does not consume any ISA DMA resources.

The IDE interface integrates 16x32-bit buffers for optimal transfers.

PIIX4’s IDE system contains two independent IDE signal channels. They can be electrically isolated

independently, allowing for the implementation of a “glueless” Swap Bay. They can be configured to the standard

primary and secondary channels (four devices) or primary drive 0 and primary drive 1 channels (two devices).

This allows flexibility in system design and device power management.

Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller)

The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven independently

programmable channels. Channels [0:3] are hardwired to 8-bit, count-by-byte transfers, and channels [5:7] are

hardwired to 16-bit, count-by-word transfers. Any two of the seven DMA channels can be programmed to

support fast Type-F transfers. The DMA controller also generates the ISA refresh cycles.

The DMA controller supports two separate methods for handling legacy DMA via the PCI bus. The PC/PCI

protocol allows PCI-based peripherals to initiate DMA cycles by encoding requests and grants via three PC/PCI

REQ#/GNT# pairs. The second method, Distributed DMA, allows reads and writes to 82C37 registers to be

distributed to other PCI devices. The two methods can be enabled concurrently. The serial interrupt scheme

typically associated with Distributed DMA is also supported.

The timer/counter block contains three counters that are equivalent in function to those found in one 82C54

programmable interval timer. These three counters are combined to provide the system timer function, refresh

request, and speaker tone. The 14.31818-MHz oscillator input provides the clock source for these three

counters.

PIIX4 provides an ISA-Compatible interrupt controller that incorporates the functionality of two 82C59 interrupt

controllers. The two interrupt controllers are cascaded so that 14 external and two internal interrupts are

possible. In addition, PIIX4 supports a serial interrupt scheme. PIIX4 provides full support for the use of an

external IO APIC.

All of the registers in these modules can be read and restored. This is required to save and restore system state

after power has been removed and restored to the circuit.

Enhanced Universal Serial Bus (USB) Controller

The PIIX4 USB controller provides enhanced support for the Universal Host Controller Interface (UHCI). This

includes support that allows legacy software to use a USB-based keyboard and mouse.

82371AB Datasheet(PDF) 13 Page - Intel Corporation

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