82371AB datasheet(56/284 Pages) INTEL

56 / 284 page

82371AB (PIIX4)

4/9/97 2:23 PM PIIX4aDS

INTEL CONFIDENTIAL

(until publication date)

PRELIMINARY

4.1.6.

CLASSC—CLASS CODE REGISTER (FUNCTION 0)

Address Offset:

−0Bh

Default Value:

060100h

Attribute:

Read Only

This register identifies the Base Class Code, Sub-Class Code, and Device Programming interface for PIIX4 PCI

function 0.

Bit

Description

23:16

Base Class Code (BASEC). 06h=Bridge device.

15:8

Sub-Class Code (SCC). 01h=PCI-to-ISA Bridge. 80h=Other bridge Device (PCI Positive Decode

Bridge). This value depends upon the programming of bit 1 of the General Configuration register

(PCI function 0, address B0h). If programmed as a Subtractive Decode bridge (default), this will read

01h. If programmed as a Positive Decode bridge, this will read 80h.

7:0

Programming Interface (PI). 00h=No register level programming interface defined.

4.1.7.

HEDT—HEADER TYPE REGISTER (FUNCTION 0)

Address Offset:

0Eh

Default Value:

80h

Attribute:

Read Only

The HEDT Register identifies PIIX4 as a multi-function device.

Bit

Description

7:0

Device Type (DEVICET). 80h=multi-function device.

4.1.8.

IORT—ISA I/O RECOVERY TIMER REGISTER (FUNCTION 0)

Address Offset:

4Ch

Default Value:

4Dh

Attribute:

Read/Write

The I/O recovery mechanism in PIIX4 is used to add additional recovery delay between CPU or PCI master

originated 8-bit and 16-bit I/O cycles to the ISA Bus. PIIX4 automatically forces a minimum delay of

3.5 SYSCLKs between back-to-back 8- and 16-bit I/O cycles to the ISA Bus. This delay is measured from the

rising edge of the I/O command (IOR# or IOW#) to the falling edge of the next I/O command. If a delay of greater

than 3.5 SYSCLKs is required, the ISA I/O Recovery Time Register can be programmed to increase the delay in

increments of SYSCLKs. No additional delay is inserted for back-to-back I/O “sub cycles” generated as a result

of byte assembly or disassembly. This register defaults to 8- and 16-bit recovery enabled with one SYSCLK

clock added to the standard I/O recovery.

82371AB Datasheet(PDF) 56 Page - Intel Corporation

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