82371AB datasheet(25/284 Pages) INTEL

25 / 284 page

82371AB (PIIX4)

4/9/97 2:23 PM PIIX4aDS

INTEL CONFIDENTIAL

(until publication date)

PRELIMINARY

Name

Type

Description

IRQ 3:7, 9:11,

14:15

INTERRUPT REQUESTS 3:7, 9:11, 14:15. The IRQ signals provide both system

board components and ISA Bus I/O devices with a mechanism for asynchronously

interrupting the CPU. These interrupts may be programmed for either an edge

sensitive or a high level sensitive assertion mode. Edge sensitive is the default

configuration.

An active IRQ input must remain asserted until after the interrupt is acknowledged. If

the input goes inactive before this time, a default IRQ7 is reported in response to the

interrupt acknowledge cycle.

IRQ8#/

GPI6

I/O

IRQ 8#. IRQ8# is always an active low edge triggered interrupt and can not be

modified by software.

IRQ8# must remain asserted until after the interrupt is acknowledged. If the input

goes inactive before this time, a default IRQ7 is reported in response to the interrupt

acknowledge cycle.

If using the internal RTC, then this can be programmed as a general-purpose input. If

enabling an APIC, this signal becomes an output and must not be programmed as a

general purpose input.

IRQ9OUT#/

GPO29

IRQ9OUT#. IRQ9OUT# is used to route the internally generated SCI and SMBus

interrupts out of the PIIX4 for connection to an external IO APIC. If APIC is disabled,

this signal pin is a General Purpose Output.

During Reset: High

After Reset: High

During POS: IRQ9OUT#/GPO

IRQ 12/M

INTERRUPT REQUEST 12. In addition to providing the standard interrupt function

as described in the pin description for IRQ[3:7,9:11,14:15], this pin can also be

programmed to provide the mouse interrupt function.

When the mouse interrupt function is selected, a low to high transition on this signal

is latched by PIIX4 and an INTR is generated to the CPU as IRQ12. An internal

IRQ12 interrupt continues to be generated until a Reset or an I/O read access to

address 60h (falling edge of IOR#) is detected.

PIRQ[A:D]#

I/OD

PCI

PROGRAMMABLE INTERRUPT REQUEST. The PIRQx# signals are active low,

level sensitive, shareable interrupt inputs. They can be individually steered to ISA

interrupts IRQ [3:7,9:12,14:15]. The USB controller uses PIRQD# as its output

signal.

SERIRQ/

GPI7

I/O

SERIAL INTERRUPT REQUEST. Serial interrupt input decoder, typically used in

conjunction with the Distributed DMA protocol.

If not using serial interrupts, this pin can be used as a general-purpose input.

82371AB Datasheet(PDF) 25 Page - Intel Corporation

82371AB Datasheet(HTML) 25 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL