82371AB datasheet(67/284 Pages) INTEL

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82371AB (PIIX4)

4/9/97 2:23 PM PIIX4aDS

INTEL CONFIDENTIAL

(until publication date)

PRELIMINARY

Bit

Description

Positive or Subtractive Decode Configuration. 0=Subtractive Decode (default). 1=Positive

Decode. This bit determines how PIIX4 decodes accesses on the PCI bus for forwarding to ISA.

If set for positive decode, PIIX4 positively decodes (with medium decode timing) and forwards PCI

access to ISA only for address ranges which are enabled within PIIX4. If set for subtractive decode,

PIIX4 positively decodes and forwards those cycles whose addresses are enabled within PIIX4. It

subtractively decodes and forwards all other cycles not positively decoded by another device on the

PCI bus. The setting and functionality of this bit is independent of bit 0, ISA or

EIO Select.

ISA or EIO Select. 0=EIO (default). 1=ISA. This bit determines whether the expansion bus on PIIX4

supports the full Industry Standard Architecture (ISA) bus or whether it supports the Extended I/O

(EIO) bus. See the ISA/EIO Interface section for details concerning ISA and EIO interface

differences.

This bit also selects the functionality multiplexed onto the IOCHK# and LA[17:23] pins. 0=GPI0 and

GPO[1:7] (default). 1=IOCHK# and LA[17:23] respectively. These are the signals which are not used

in EIO mode.

4.1.20.

RTCCFG—REAL TIME CLOCK CONFIGURATION REGISTER (FUNCTION 0)

Address Offset:

CBh

Default Value:

21h

Attribute:

Read/Write

This register is used to configure the internal Real Time Clock.

Bit

Description

7:6

Reserved.

RTC Positive Decode Enable. 0=PIIX4 Subtractively Decodes for RTC I/O registers. 1=PIIX4

Positively Decodes for RTC I/O registers (default). The PCI cycles with addresses 70–73h are either

positively or subtractively decoded based on this bit. The cycles are then routed to the internal RTC

controller or forwarded to ISA based on bits 2 (extended bank) and bit 0 (standard bank) below.

This bit should be set to 0 if PIIX4’s internal RTC is not used and the external RTC is on the

PCI bus, or if subtractive decode is desired for an external RTC on the ISA or X-Bus.

Lock Upper RAM Bytes. 0=Upper RAM data bytes 38h–3Fh in the extended bank are readable and

writeable (default). 1=Upper RAM data bytes 38h–3Fh in the extended bank are neither readable nor

writeable. This is used to lock bytes 38h–3Fh in the upper 128-byte bank of RAM. Write cycles will

have no effect and read cycles will not return a guaranteed value.

Warning: This is a write-once register that can only be reset by a hardware reset. No software

means is possible to reset this bit.

Lock Lower RAM Bytes. 0=Lower RAM data bytes 38h–3Fh in the standard bank are readable and

writeable (default). 1=Lower RAM data bytes 38h–3Fh in the standard bank are neither readable nor

writeable. This is used to lock bytes 38h–3Fh in the lower 128-byte bank of RAM. Write cycles will

have no effect and read cycles will not return a guaranteed value.

Warning: This is a write-once register that can only be reset by a hardware reset. No software

means is possible to reset this bit.

82371AB Datasheet(PDF) 67 Page - Intel Corporation

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