82371AB datasheet(22/284 Pages) INTEL

22 / 284 page

82371AB (PIIX4)

4/9/97 2:23 PM PIIX4aDS

INTEL CONFIDENTIAL

(until publication date)

PRELIMINARY

Name

Type

Description

RTCALE/

GPO25

REAL TIME CLOCK ADDRESS LATCH ENABLE. RTCALE is used to latch the

appropriate memory address into the RTC. A write to port 70h with the appropriate RTC

memory address that will be written to or read from causes RTCALE to be asserted.

RTCALE is asserted on falling IOW# and remains asserted for two SYSCLKs.

If the internal Real Time Clock is used, this signal can be programmed as a general

purpose output.

During Reset: Low

After Reset: Low

During POS: Low/GPO

RTCCS#/

GPO24

REAL TIME CLOCK CHIP SELECT. RTCCS# is asserted during read or write I/O

accesses to RTC location 71h. RTCCS# can be tied to a pair of external OR gates to

generate the real time clock read and write command signals. If the internal Real Time

Clock is used, this signal can be programmed as a general purpose output.

During Reset: High

After Reset: High

During POS: High/GPO

XDIR#/

GPO22

X-BUS TRANSCEIVER DIRECTION. XDIR# is tied directly to the direction control of a

74’245 that buffers the X-Bus data, XD[7:0]. XDIR# is asserted (driven low) for all I/O

read cycles regardless if the accesses is to a PIIX4 supported device. XDIR# is

asserted for memory cycles only if BIOS or APIC space has been decoded. For PCI

master initiated read cycles, XDIR# is asserted from the falling edge of either IOR# or

MEMR# (from MEMR# only if BIOS or APIC space has been decoded), depending on

the cycle type. For ISA master-initiated read cycles, XDIR# is asserted from the falling

edge of either IOR# or MEMR# (from MEMR# only if BIOS space has been decoded),

depending on the cycle type. When the rising edge of IOR# or MEMR# occurs, PIIX4

negates XDIR#. For DMA read cycles from the X-Bus, XDIR# is driven low from

DACKx# falling and negated from DACKx# rising. At all other times, XDIR# is negated

high.

If the X-Bus not used, then this signal can be programmed to be a general purpose

output.

During Reset: High

After Reset: High

During POS: High/GPO

XOE#/

GPO23

X-BUS TRANSCEIVER OUTPUT ENABLE. XOE# is tied directly to the output enable

of a 74’245 that buffers the X-Bus data, XD[7:0], from the system data bus, SD[7:0].

XOE# is asserted anytime a PIIX4 supported X-Bus device is decoded, and the devices

decode is enabled in the X-Bus Chip Select Enable Register (BIOSCS#, KBCCS#,

RTCCS#, MCCS#) or the Device Resource B (PCCS0#) and Device Resource C

(PCCS1#). XOE# is asserted from the falling edge of the ISA commands (IOR#, IOW#,

MEMR#, or MEMW#) for PCI Master and ISA master-initiated cycles. XOE# is negated

from the rising edge of the ISA command signals for PCI Master initiated cycles and the

SA[16:0] and LA[23:17] address for ISA master-initiated cycles. XOE# is not generated

during any access to an X-Bus peripheral in which its decode space has been disabled.

If an X-Bus not used, then this signal can be programmed to be a general purpose

output.

During Reset: High

After Reset: High

During POS: High/GPO

82371AB Datasheet(PDF) 22 Page - Intel Corporation

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