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82371AB Datasheet(PDF) 46 Page - Intel Corporation |
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82371AB Datasheet(HTML) 46 Page - Intel Corporation |
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46 / 284 page  82371AB (PIIX4) 46 4/9/97 2:23 PM PIIX4aDS INTEL CONFIDENTIAL (until publication date) PRELIMINARY Table 5. ISA-Compatible Registers Address Aliased Addresses Type Register Name Access 00B2h R/W Advanced Power Management Control PCI 00B3h R/W Advanced Power Management Status PCI 00C0h 00C1h R/W DMA2 CH0 Base and Current Address (CH4) PCI 00C2h 00C3h R/W DMA2 CH0 Base and Current Count (CH4) PCI 00C4h 00C5h R/W DMA2 CH1 Base and Current Address (CH5) PCI 00C6h 00C7h R/W DMA2 CH1 Base and Current Count (CH5) PCI 00C8h 00C9h R/W DMA2 CH2 Base and Current Address (CH6) PCI 00CAh 00CBh R/W DMA2 CH2 Base and Current Count (CH6) PCI 00CCh 00CDh R/W DMA2 CH3 Base and Current Address (CH7) PCI 00CEh 00CFh R/W DMA2 CH3 Base and Current Count (CH7) PCI 00D0h 00D1h R/W DMA2 Status(r) Command(w) PCI 00D2h 00D3h WO DMA2 Request PCI 00D4h 00D5h WO DMA2 Write Single Mask Bit PCI 00D6h 00D7h WO DMA2 Channel Mode PCI 00D8h 00D9h WO DMA2 Clear Byte Pointer PCI 00DAh 00DBh WO DMA2 Master Clear PCI 00DCh 00DDh WO DMA2 Clear Mask PCI 00DEh 00DFh R/W DMA2 Read/Write All Mask Register Bits PCI 00F0h 1 WO Coprocessor Error PCI/ISA 04D0h R/W INTC-1 Edge/Level Control PCI/ISA 04D1h R/W INTC-2 Edge/Level Control PCI/ISA 0CF9h R/W Reset Control PCI NOTES: 1. Read and write accesses to these locations are always broadcast to the ISA Bus. 2. Read and write accesses to these locations are broadcast to the ISA Bus, only if internal RTC is disabled in RTCCFG register. 3. Not aliased to 0072h or 0076h if extended RAM enabled. 4. Not aliased to 0073h or 0077h if extended RAM enabled. 5. The PIIX4 does not support Distributed DMA functionality for the 90h range, even if aliasing is enabled. 6. Write accesses to these locations are broadcast to the ISA Bus. Read accesses are not. If programmed in the ISA I/O Recovery Timer register, PIIX4 does not alias the entire 90h–9Fh address range. These locations are considered ISA Bus register locations and not PIIX4 registers. |
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