| Electronic Components Datasheet Search |
|
82371AB Datasheet(PDF) 49 Page - Intel Corporation |
|
|
|||||||||||||||||||||||||||||
82371AB Datasheet(HTML) 49 Page - Intel Corporation |
|
49 / 284 page ![]() 82371AB (PIIX4) 49 4/9/97 2:23 PM PIIX4aDS INTEL CONFIDENTIAL (until publication date) PRELIMINARY Table 8. PCI Configuration Registers—Function 2 (USB Interface) Address Offset Mnemonic Register Name Access 3Ch INTLN Interrupt Line R/W 3Dh INTPN Interrupt Pin RO 3E–5Fh — Reserved — 60h SBRNUM Serial Bus Release Number RO 61–BFh — Reserved — C0–C1h LEGSUP Legacy Support R/W C2–FFh — Reserved RO 3.3.2. IO SPACE REGISTERS Table 9. USB Host/Controller I/O Registers Offset From Base Address Mnemonic Register Name Access 00 −01h USBCMD USB Command R/W 2 02 −03h USBSTS USB Status R/WC 04 −05h USBINTR USB Interrupt Enable R/W 06 −07h FRNUM Frame Number R/W 2 08 −0Bh FLBASEADD Frame List Base Address R/W 0Ch SOFMOD Start Of Frame Modify R/W 10 −11h PORTSC0 Port 0 Status and Control R/WC 2 12 −13h PORTSC1 Port 1 Status and Control R/WC 2 NOTES: 1. The base address is programmable via the USBBA Register (20 −23h; function 2) 2. These registers are WORD writeable only. Byte writes to these registers have unpredictable effects. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |