82371AB datasheet(73/284 Pages) INTEL

73 / 284 page

82371AB (PIIX4)

4/9/97 2:23 PM PIIX4aDS

INTEL CONFIDENTIAL

(until publication date)

PRELIMINARY

4.2.1.9.

DLPAGE—DMA Low Page Registers (IO)

I/O Address:

DMA Channel 0—087h

DMA Channel 5—08Bh

DMA Channel 1—083h

DMA Channel 6—089h

DMA Channel 2—081h

DMA Channel 7—08Ah

DMA Channel 3—082h

Default Value:

Undefined (CPURST or Master Clear)

Attribute:

Read/Write

This register works in conjunction with the Current Address Register. After an autoinitialization, this register

retains the original programmed value. Autoinitialize takes place after a TC.

Bit

Description

7:0

DMA Low Page [23:16]. These bits represent address bits [23:16] of the 24-bit DMA address.

4.2.1.10.

DCBP—DMA Clear Byte Pointer Register (IO)

I/O Address:

Channels 0–3—00Ch; Channels 4–7—0D8h

Default Value:

All bits undefined

Attribute:

Write Only

Writing to this register executes the Clear Byte Pointer Command. This command is executed prior to

reading/writing a new address or word count to the DMA. The command initializes the byte pointer flip-flop to a

known state so that subsequent accesses to register contents address upper and lower bytes in the correct

sequence. The Clear Byte Pointer Command (or CPURST or the Master Clear Command) clears the internal

latch used to address the upper or lower byte of the 16-bit Address and Word Count Registers.

Bit

Description

7:0

Clear Byte Pointer. No specific pattern. Command enabled with a write to the I/O port address.

4.2.1.11.

DMC—DMA Master Clear Register (IO)

I/O Address:

Channel 0–3—00Dh; Channel 4–7—0DAh

Default Value:

All bits undefined

Attribute:

Write Only

This software instruction has the same effect as the hardware Reset.

Bit

Description

7:0

Master Clear. No specific pattern. Command enabled with a write to the I/O port address.

82371AB Datasheet(PDF) 73 Page - Intel Corporation

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